Thanks for all the reviews! I’ve revised the patch, the operator_delete_flag is
now stored in tree_decl_with_vis (there already seem to be some
FUNCTION_DECL-flags in there). I’ve also added the option -fallocation-dce to
disable this optimization. It bootstraps and no regressions on aarch64 and
1/21/2017 04:14 AM, Dominik Inführ wrote:
>> Hi,
>>
>> this patch tries to extend tree-ssa-dce.c to remove unnecessary
>> new/delete-pairs (it already does that for malloc/free). Clang does it too
>> and it seems to be allowed by
>> http://www.open-std.org/jtc
Hi,
this patch tries to extend tree-ssa-dce.c to remove unnecessary
new/delete-pairs (it already does that for malloc/free). Clang does it too and
it seems to be allowed by
http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2013/n3664.html. I’ve
bootstrapped/regtested on aarch64-linux and x86_
Thanks for the review! Could you also please commit this patch for me? I don’t
have commit rights.
Thanks,
Dominik
> On 17 Nov 2017, at 23:18, James Greenhalgh wrote:
>
> On Tue, Oct 31, 2017 at 02:47:29PM +0100, Dominik Inführ wrote:
>> Hi,
>>
>> I have a cus
Could you please commit it for me? I don’t have commit rights.
Thanks,
Dominik
> On 13 Nov 2017, at 12:27, Kyrill Tkachov wrote:
>
>
> On 13/11/17 11:09, Dominik Inführ wrote:
>> Oh sure, I've now successfully bootstrapped on arm-linux-gnueabihf and
>&
Oh sure, I've now successfully bootstrapped on arm-linux-gnueabihf and
aarch64-unknown-linux-gnu.
Dominik
> On 10 Nov 2017, at 10:53, Kyrill Tkachov wrote:
>
> Hi Dominic,
>
> On 10/11/17 09:36, Dominik Inführ wrote:
>> Hi,
>>
>> this patch tries to r
Ping
> On 31 Oct 2017, at 14:47, Dominik Inführ
> wrote:
>
> Hi,
>
> I have a custom optimization pass, that moves an expression into an
> POST_INC-expression. GCC then ICE’s in df-scan.c since it expects REG_P to be
> true for POST_INC’s operand. aarch64_simd_mem_o
> On 10 Nov 2017, at 10:40, James Greenhalgh wrote:
>
> On Fri, Nov 10, 2017 at 10:36:57AM +0100, Dominik Inführ wrote:
>> Hi,
>>
>> this patch tries to refine the instruction scheduling model for X-Gene.
>> Improved performance for 456.hmmer and 464.h264r
Hi,
this patch tries to refine the instruction scheduling model for X-Gene.
Improved performance for 456.hmmer and 464.h264ref (about 1%). Also splits the
model into multiple automatons, therefore smaller binary and faster build time.
Survives bootstrap.
Best,
Dominik
gcc/ChangeLog:
2017-10-0
> On 31 Oct 2017, at 15:47, Kyrill Tkachov wrote:
>
>
> On 31/10/17 14:44, Dominik Inführ wrote:
>>> On 31 Oct 2017, at 15:10, Kyrill Tkachov
>>> wrote:
>>>
>>> [cc'ing aarch64 maintainers]
>>>
>>> Hi Dominik,
>>
> On 31 Oct 2017, at 15:10, Kyrill Tkachov wrote:
>
> [cc'ing aarch64 maintainers]
>
> Hi Dominik,
>
> On 31/10/17 13:47, Dominik Inführ wrote:
>> Hi,
>>
>> I have a custom optimization pass, that moves an expression into an
>> POST_IN
Hi,
I have a custom optimization pass, that moves an expression into an
POST_INC-expression. GCC then ICE’s in df-scan.c since it expects REG_P to be
true for POST_INC’s operand. aarch64_simd_mem_operand_p doesn’t seem to check
POST_INC’s operand. Here is a patch that fixes this for me, althoug
Could you please also commit the patch? I don’t have commit rights.
Best
Dominik
> On 24 Oct 2017, at 16:58, Richard Earnshaw (lists)
> wrote:
>
> On 24/10/17 15:54, Dominik Inführ wrote:
>>
>>> On 24 Oct 2017, at 11:40, Richard Earnshaw (lists)
>>>
> On 24 Oct 2017, at 11:40, Richard Earnshaw (lists)
> wrote:
>
> On 23/10/17 17:36, Dominik Inführ wrote:
>> I’ve added your suggestions. I would also like to propose to change the type
>> attribute from neon_stp to store_8 and store_16, this seems to be more in
store1_1reg,\
+neon_logic, multiple, multiple,\
multiple, neon_move")
(set_attr "length" "4,4,4,4,8,8,8,4")]
)
> On 20 Oct 2017, at 16:07, Richard Earnshaw (lists)
> wrote:
>
> On 16/10/17 14:26, Domini
Hi,
it seems the type attributes for neon_stp and neon_store1_1reg should be the
other way around.
Thanks
Dominik
ChangeLog:
2017-10-16 Dominik Infuehr
* config/aarch64/aarch64-simd.md
(*aarch64_simd_mov): Fix type-attribute.
--
diff --git a/gcc/config/aarch64/aarch64-simd.m
tree_life.safe_splice (*life);
+ scalar_cost += vect_bb_slp_scalar_cost (bb, child, &subtree_life);
+ subtree_life.truncate (0);
+ }
return scalar_cost;
}
> On 04 Aug 2017, at 12:19, Richard Biener wrote:
>
> On Fri, Aug 4, 2017 at 12:08 PM, Dominik Inführ
> wro
Hi,
vect_bb_slp_scalar_cost computes the scalar cost of a SLP node. If there are
non-scalar uses of a definition, the costs for it and its operands (children)
are ignored. The vector LIFE is used to keep track of this and an element is
set to true, such that the def and its children are ignored
I am not sure about the process, but it may also be nice/useful to add your new
macro to ForEachMacros in contrib/clang-format.
Dominik
> On 07 Sep 2016, at 02:21, Kugan Vivekanandarajah
> wrote:
>
> Hi Richard,
>
> On 6 September 2016 at 19:08, Richard Biener
> wrote:
>> On Tue, Sep 6, 20
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