On 2024-07-09 01:49 Jeff Law wrote:
>
>
>
>On 7/8/24 2:39 AM, Fei Gao wrote:
>> Root cause:
>> https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=b27d323a368033f0b37e93c57a57a35fd9997864
>> Commit above tries in targetm.gen_epilogue () to detect if
>> there's l
rget/riscv/rvv/base/abi-callee-saved-2-zcmp.c: likewise.
* gcc.target/riscv/rvv/base/pr114352-1.c: likewise.
* gcc.target/riscv/rvv/base/pr114352-3.c: likewise.
* gcc.target/riscv/arch-39.c: New test.
* gcc.target/riscv/arch-40.c: New test.
Signed-off-by: Fei
On 2024-07-09 01:49 Jeff Law wrote:
>Has the ESWIN team ever considered doing a bootstrap test of the zcmp*
>extensions? ie, turn them all on by default, then build GCC natively on
>an rv32 system (or qemu emulated rv32 system)?
>
>I've found that kind of test amazingly helpful through the
the assignment to a0 and use insn with cm.popret.
That's likely going to result in some kind of code size regression,
but not a correctness regression.
Optimization can be done in future.
Signed-off-by: Fei Gao
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_zcmp_can_use_popretz): Removed
On 2024-07-07 22:53 Jeff Law wrote:
>
>
>
>On 6/8/24 2:36 PM, Jeff Law wrote:
>>
>>
>> On 6/5/24 8:42 PM, Fei Gao wrote:
>>
>>>> But let's back up and get a good explanation of what the problem is.
>>>> Based on patch 2/2 it looks
On 2024-07-06 22:15 Jeff Law wrote:
>
>
>
>On 7/5/24 3:56 AM, Fei Gao wrote:
>> According to Zc-1.0.4-3.pdf from
>> https://github.com/riscvarchive/riscv-code-size-reduction/releases/tag/v1.0.4-3
>> The rule is that:
>> 1. C always implies Zca
>> 2. C+F
rget/riscv/rvv/base/abi-callee-saved-2-zcmp.c: likewise.
* gcc.target/riscv/rvv/base/pr114352-1.c: likewise.
* gcc.target/riscv/rvv/base/pr114352-3.c: likewise.
* gcc.target/riscv/arch-39.c: New test.
* gcc.target/riscv/arch-40.c: New test.
Signed-off-by: Fei
added.
(riscv_subset_list::finalize): call handle_implied_ext repeatly
until no change in m_subset_num.
* config/riscv/riscv-subset.h: add m_subset_num member.
Signed-off-by: Fei Gao
---
gcc/common/config/riscv/riscv-common.cc | 14 +++---
gcc/config/riscv/riscv
with no new failures.
Fei Gao (2):
[RISC-V] add impied extension repeatly until stable
[RISC-V] c impies zca, and conditionally zcf & zcd
gcc/common/config/riscv/riscv-common.cc | 26 ---
gcc/config/riscv/riscv-subset.h | 3 +++
gcc/testsuite/gcc.target/riscv/
On 2024-06-09 04:36 Jeff Law wrote:
>
>
>
>On 6/5/24 8:42 PM, Fei Gao wrote:
>
>>> But let's back up and get a good explanation of what the problem is.
>>> Based on patch 2/2 it looks like we have lost an assignment to the
>>> return register.
>
Hi Jin
We have completed zvfbfmin and zvfbfwma in GCC.
Wang Feng will post after dragon boat festival.
BR,
Fei
From: Jin Ma
Date: 2024-06-07 15:35
To: gcc-patches; zengxiao
CC: jeffreyalaw; kito.cheng; juzhe.zhong; jinma.contrib; Jin Ma
Subject: [RE] [v2] RISC-V: Add Zfbfmin extension
Hi,
On 2024-06-05 21:58 Jeff Law wrote:
>
>
>
>On 6/5/24 1:47 AM, Fei Gao wrote:
>>
>> On 2024-06-05 14:36 Kito Cheng wrote:
>>>
>>> Thanks for fixing this issue, and I am wondering doest it possible to
>>> fix that without introduce target hook
ear logic.
BR
Fei
>
>On Wed, Jun 5, 2024 at 9:50 AM Fei Gao wrote:
>>
>> The 1st patch adds a hook to allow post processing after epilogue inserted.
>> The 2nd one implement the RISC-V hook to solve PR113715.
>>
>> Fei Gao (2):
>> target hooks: allow post
targets to have additional processingafter epilogue is
inserted into a basic block.
* hooks.cc (hook_void_rtx_insn): Define default handler.
* hooks.h (hook_void_rtx_insn): Declare.
* target.def: New hook.
Signed-off-by: Fei Gao
---
gcc/doc/tm.texi| 5
): Implement TARGET_POST_EPILOGUE_PROC.
(TARGET_POST_EPILOGUE_PROC): Define RISC-V hook.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rv32i_zcmp.c: New case.
Signed-off-by: Fei Gao
---
gcc/config/riscv/riscv.cc | 191 ++--
gcc/testsuite/gcc.target/riscv
The 1st patch adds a hook to allow post processing after epilogue inserted.
The 2nd one implement the RISC-V hook to solve PR113715.
Fei Gao (2):
target hooks: allow post processing after epilogue inserted.
[RISC-V]: fix zcmp popretz [PR113715].
gcc/config/riscv/riscv.cc
Committed. Thanks Kito and Jeff for the reveiw.
BR
Fei
>
>
>On 4/15/24 7:27 PM, Fei Gao wrote:
>> On 2024-04-15 21:04 Jeff Law wrote:
>>>
>>>
>>>
>>> On 4/15/24 6:58 AM, Kito Cheng wrote:
>>>> It's simple enough, so LGTM for t
On 2024-04-15 21:04 Jeff Law wrote:
>
>
>
>On 4/15/24 6:58 AM, Kito Cheng wrote:
>> It's simple enough, so LGTM for trunk :)
>We're already doing this internally. I just hadn't submitted it due to
>being deep into stage4.
>
>Jeff
Hi Jeff
Would you like me to commit it now or leave it to you
When one of the two input operands is 0, ADD and IOR are functionally
equivalent.
ADD is slightly preferred over IOR because ADD has a higher likelihood
of being implemented as a compressed instruction when compared to IOR.
C.ADD uses the CR format with any of the 32 RVI registers availble,
while
On 2023-12-25 16:45 Kito Cheng wrote:
>+++ b/gcc/testsuite/gcc.target/riscv/interrupt-misaligned.c
>@@ -0,0 +1,29 @@
>+/* { dg-do compile } */
>+/* { dg-options "-O2 -march=rv64gc -mabi=lp64d -fno-schedule-insns
>-fno-schedule-insns2" } */
>+/* { dg-skip-if "" { *-*-* } { "-flto
On 2023-12-11 13:46 Jeff Law wrote:
>
>
>
>On 12/5/23 01:12, Fei Gao wrote:
>> SIGN_EXTEND, ZERO_EXTEND and SUBREG has been considered
>> to support SImode in 64-bit machine.
>>
>> Co-authored-by: Xiao Zeng
>>
>> gcc/ChangeLog:
>>
>>
On 2023-12-11 13:38 Jeff Law wrote:
>
>
>
>On 12/5/23 01:12, Fei Gao wrote:
>> op=[PLUS, MINUS, IOR, XOR, ASHIFT, ASHIFTRT, LSHIFTRT, ROTATE, ROTATERT, AND]
>>
>> Co-authored-by: Xiao Zeng
>>
>> gcc/ChangeLog:
>>
>> * ifcvt.cc (noce_
On 2023-12-11 04:43 Jeff Law wrote:
>
>
>
>On 12/5/23 01:12, Fei Gao wrote:
>> op=[ASHIFT, ASHIFTRT, LSHIFTRT, ROTATE, ROTATERT]
>>
>> Conditional op, if zero
>> rd = (rc == 0) ? (rs1 op rs2) : rs1
>> -->
>> czero.nez rd, rs2, rc
>> op
On 2023-11-29 19:09 Fei Gao wrote:
>
>On 2023-11-29 13:26 Jeff Law wrote:
>>
>>
>>
>>On 11/27/23 19:32, Fei Gao wrote:
>>> op=[PLUS, MINUS, IOR, XOR, ASHIFT, ASHIFTRT, LSHIFTRT, ROTATE, ROTATERT]
>>>
>>> SIGN_EXTEND, ZERO_EXTEND and S
SIGN_EXTEND, ZERO_EXTEND and SUBREG has been considered
to support SImode in 64-bit machine.
Co-authored-by: Xiao Zeng
gcc/ChangeLog:
* ifcvt.cc (noce_cond_zero_binary_op_supported): add support for
extension
(noce_bbs_ok_for_cond_zero_arith): likewise
op=[PLUS, MINUS, IOR, XOR, ASHIFT, ASHIFTRT, LSHIFTRT, ROTATE, ROTATERT, AND]
Co-authored-by: Xiao Zeng
gcc/ChangeLog:
* ifcvt.cc (noce_cond_zero_shift_op_supported): check if OP is shift
like operation
(noce_cond_zero_binary_op_supported): restructure & call
Take the following case for example.
CFLAGS: -march=rv64gc_zbb_zicond -mabi=lp64d -O2
long
test_AND_ceqz (long x, long y, long z, long c)
{
if (c)
x = y & z;
else
x = y;
return x;
}
Before patch:
and a2,a1,a2
czero.eqz a0,a2,a3
czero.nez a3,a1,a3
or a0,a3,a0
op=[ASHIFT, ASHIFTRT, LSHIFTRT, ROTATE, ROTATERT]
Conditional op, if zero
rd = (rc == 0) ? (rs1 op rs2) : rs1
-->
czero.nez rd, rs2, rc
op rd, rs1, rd
Conditional op, if non-zero
rd = (rc != 0) ? (rs1 op rs2) : rs1
-->
czero.eqz rd, rs2, rc
op rd, rs1, rd
Co-authored-by: Xiao Zeng
op=[PLUS, MINUS, IOR, XOR]
Conditional op, if zero
rd = (rc == 0) ? (rs1 op rs2) : rs1
-->
czero.nez rd, rs2, rc
op rd, rs1, rd
Conditional op, if non-zero
rd = (rc != 0) ? (rs1 op rs2) : rs1
-->
czero.eqz rd, rs2, rc
op rd, rs1, rd
Co-authored-by: Xiao Zeng
gcc/ChangeLog:
* ifcvt.cc
Committed! Thanks Kito.
BR,
Fei
On 2023-12-04 15:01 Kito Cheng wrote:
>
>LGTM again :)
>
>On Mon, Dec 4, 2023 at 2:44 PM Feng Wang wrote:
>>
>> Rebase and resend this patch due to it was not added into patchwork
>> before. Kito had already reviewed it. Please refer to
>>
Committed. Thanks Kito and Jeff.
BR
Fei
On 2023-11-28 13:03 Jeff Law wrote:
>
>
>
>On 11/27/23 20:09, Kito Cheng wrote:
>> Personally I don't like to play with the pattern order to tweak the
>> code gen since it kinda introduces implicit relation/rule here, but I
>> guess the only way to
On 2023-11-29 13:26 Jeff Law wrote:
>
>
>
>On 11/27/23 19:32, Fei Gao wrote:
>> op=[PLUS, MINUS, IOR, XOR, ASHIFT, ASHIFTRT, LSHIFTRT, ROTATE, ROTATERT]
>>
>> SIGN_EXTEND, ZERO_EXTEND and SUBREG has been considered
>> to support SImode in 64-bit machine
hi Jeff and Kito
Please be noted this patch is based on
https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg327149.html
[PATCH 3/4] [ifcvt] optimize x=c ? (y op const_int) : y by RISC-V Zicond like
insns
Thanks & BR,
Fei
On 2023-11-28 18:10 Fei Gao wrote:
>
>Take the foll
Take the following case for example.
CFLAGS: -march=rv64gc_zbb_zicond -mabi=lp64d -O2
long
test_AND_ceqz (long x, long y, long z, long c)
{
if (c)
x = y & z;
else
x = y;
return x;
}
Before patch:
and a2,a1,a2
czero.eqz a0,a2,a3
czero.nez
On 2023-11-20 15:10 Jeff Law wrote:
>
>
>
>On 10/30/23 01:25, Fei Gao wrote:
>
>> diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc
>> index 6e341fc4d4b..cfa9bc4b850 100644
>> --- a/gcc/ifcvt.cc
>> +++ b/gcc/ifcvt.cc
>> @@ -2911,7 +2911,7 @@ noce_try_sign_ma
On 2023-11-20 14:59 Jeff Law wrote:
>
>
>
>On 10/30/23 01:25, Fei Gao wrote:
>> Conditional add, if zero
>> rd = (rc == 0) ? (rs1 + rs2) : rs1
>> -->
>> czero.nez rd, rs2, rc
>> add rd, rs1, rd
>>
>> Conditional add, if non-zero
>>
On 2023-11-20 14:46 Jeff Law wrote:
>
>
>
>On 10/30/23 21:35, Fei Gao wrote:
>
>>> So just a few notes to further illustrate why I'm currently looking to
>>> take the VRULL+Ventana implementation. The code above would be much
>>> better handled by just
op=[PLUS, MINUS, IOR, XOR, ASHIFT, ASHIFTRT, LSHIFTRT, ROTATE, ROTATERT]
SIGN_EXTEND, ZERO_EXTEND and SUBREG has been considered
to support SImode in 64-bit machine.
Conditional op, if zero
rd = (rc == 0) ? (rs1 op rs2) : rs1
-->
czero.nez rd, rs2, rc
op rd, rs1, rd
Conditional op, if non-zero
In x=c ? (y op CONST) : y cases, Zicond based czero ifcvt generates
more true dependency in code sequence than SFB based movcc. So exit
noce_try_cond_zero_arith in such cases to have a better code sequence
generated by noce_try_cmove_arith.
Take the following case for example.
CFLAGS:
op=[PLUS, MINUS, IOR, XOR, ASHIFT, ASHIFTRT, LSHIFTRT, ROTATE, ROTATERT]
Co-authored-by: Xiao Zeng
gcc/ChangeLog:
* ifcvt.cc (noce_cond_zero_shift_op_supported): check if OP is shift
like operation
(noce_cond_zero_binary_op_supported): restructure & call
Move Zicond md files ahead of SFB to recognize Zicond first.
Take the following case for example.
CFLAGS: -mtune=sifive-7-series -march=rv64gc_zicond -mabi=lp64d
long primitiveSemantics_00(long a, long b) { return a == 0 ? 0 : b; }
before patch:
primitiveSemantics_00:
bne
On 2023-10-31 03:16 Jeff Law wrote:
>
>
>
>On 10/30/23 01:25, Fei Gao wrote:
>> Conditional add, if zero
>> rd = (rc == 0) ? (rs1 + rs2) : rs1
>> -->
>> czero.nez rd, rs2, rc
>> add rd, rs1, rd
>>
>> Conditional add, if non-zero
>>
On 2023-10-31 00:36 Jeff Law wrote:
>
>
>
>On 10/30/23 01:25, Fei Gao wrote:
>> Conditional add, if zero
>> rd = (rc == 0) ? (rs1 + rs2) : rs1
>> -->
>> czero.nez rd, rs2, rc
>> add rd, rs1, rd
>>
>> Conditional add, if non-zero
>>
On 2023-10-28 10:35 Jeff Law wrote:
>
>
>
>On 10/27/23 14:31, Patrick O'Neill wrote:
>> Hi Fei,
>>
>> A recent change to GCC [1] updated the the registers in the cm.push and
>> cm.pop insns for these testcases:
>>
>> |FAIL: gcc.target/riscv/rv32i_zcmp.c -Os check-function-bodies test1
>>
op=[-, |, ^]
opcode=[sub, or, xor]
Conditional op, if zero
rd = (rc == 0) ? (rs1 op rs2) : rs1
-->
czero.nez rd, rs2, rc
opcode rd, rs1, rd
Conditional op, if non-zero
rd = (rc != 0) ? (rs1 op rs2) : rs1
-->
czero.eqz rd, rs2, rc
opcode rd, rs1, rd
Co-authored-by: Xiao Zeng
gcc/ChangeLog:
Conditional and, if zero
rd = (rc == 0) ? (rs1 & rs2) : rs1
-->
and rd, rs1, rs2
czero.eqz rtmp, rs1, rc
or rd, rd, rtmp
Conditional and, if non-zero
rd = (rc != 0) ? (rs1 & rs2) : rs1
-->
and rd, rs1, rs2
czero.nez rtmp, rs1, rc
or rd, rd, rtmp
Co-authored-by: Xiao Zeng
gcc/ChangeLog:
Conditional add, if zero
rd = (rc == 0) ? (rs1 + rs2) : rs1
-->
czero.nez rd, rs2, rc
add rd, rs1, rd
Conditional add, if non-zero
rd = (rc != 0) ? (rs1 + rs2) : rs1
-->
czero.eqz rd, rs2, rc
add rd, rs1, rd
Co-authored-by: Xiao Zeng
gcc/ChangeLog:
* ifcvt.cc (noce_emit_czero): helper
ro
rd = (rc != 0) ? (rs1 & rs2) : rs1
-->
and rd, rs1, rs2
czero.nez rtmp, rs1, rc
or rd, rd, rtmp
Fei Gao (4):
[RISC-V]add hook to control Zicond based ifcvt opt
[ifcvt] if convert x=c ? y+z : y by RISC-V Zicond like insns
[ifcvt] if convert x=c ?
TARGET_HAVE_COND_ZERO is added to control ifcvt optimization
for targets with RISC-V Zicond like insns.
Co-authored-by: Xiao Zeng
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_have_cond_zero): Implement
TARGET_HAVE_COND_ZERO
(TARGET_HAVE_COND_ZERO): define RISC-V hook
*
Signed-off-by: Fei Gao
ChangeLog:
* MAINTAINERS: Add myself.
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f2f5ed29885..e9154878517 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -424,6 +424,7 @@ Gary Funck
The code changes are from Palmer.
root cause:
In a gcc build with --enable-checking=yes, REGNO (op) checks
rtx code and expected code 'reg'. so a rtx with 'subreg' causes
an internal compiler error.
solution:
Restrict predicate to allow 'reg' only.
gcc/ChangeLog:
*
On 2023-09-06 16:06 Kito Cheng wrote:
>
>On Wed, Sep 6, 2023 at 9:47 AM Fei Gao wrote:
>>
>> On 2023-09-05 20:02 Kito Cheng wrote:
>> >
>> >> @@ -5569,7 +5571,9 @@ riscv_avoid_multi_push (const struct
>> >> riscv_frame_info *frame)
>>
REGNO (op), S0_REGNUM,
>S1_REGNUM)
> : IN_RANGE (REGNO (op), S0_REGNUM, S1_REGNUM)
> || IN_RANGE (REGNO (op), S2_REGNUM, S7_REGNUM)")))
>
>> Regards,
>> Dimitar
>>
>> On Tue, Aug 29, 2023 at 08:37:46AM +, Fei Gao w
So that zcmp can be enabled in -Os where
shrink-wrap-separate is not effective.
To force enabling zcmp multi push/pop in speed perfered case,
fno-shrink-wrap-separate has to be explictly given.
gcc/ChangeLog:
* config/riscv/riscv.cc
(riscv_avoid_shrink_wrapping_separate): wrap
No functional changes but restructure and expose use_shrink_wrapping_separate
to the TARGETs.
gcc/ChangeLog:
* shrink-wrap.cc (try_shrink_wrapping_separate):call
use_shrink_wrapping_separate.
(use_shrink_wrapping_separate): wrap the condition
check in
Enable muti push and pop for Zcmp when shrink-wrap-separate is ineffective.
Fei Gao (2):
allow targets to check shrink-wrap-separate enabled or not
[V2][RISC-V] enable muti push and pop for Zcmp when shrink-wrap-separate is
ineffective
gcc/config/riscv/riscv.cc | 21
On 2023-09-05 20:02 Kito Cheng wrote:
>
>> @@ -5569,7 +5571,9 @@ riscv_avoid_multi_push (const struct riscv_frame_info
>> *frame)
>> {
>> if (!TARGET_ZCMP || crtl->calls_eh_return || frame_pointer_needed
>> || cfun->machine->interrupt_handler_p || cfun->machine->varargs_size
>>!= 0
On 2023-08-29 09:46 Jeff Law wrote:
>
>
>
>On 8/28/23 19:28, Fei Gao wrote:
>> On 2023-08-29 06:54 Jeff Law wrote:
>>>
>>>
>>>
>>> On 8/28/23 01:47, Fei Gao wrote:
>>>> no functional changes but allow targets to check shrin
Enalble zcmp for -Os and shrink-warp-separate for
the speed perfered optimization by default.
To force enabling zcmp multi push/pop in speed perfered case,
fno-shrink-wrap-separate has to be explictly given.
gcc/ChangeLog:
* config/riscv/riscv.cc
Enalble zcmp for -Os and shrink-warp-separate for
the speed perfered optimization by default.
Fei Gao (2):
allow targets to check shrink-wrap-separate enabled or not
[RISC-V] Enalble zcmp for -Os
gcc/config/riscv/riscv.cc | 21 -
gcc/shrink-wrap.cc
No functional changes but restructure and expose use_shrink_wrapping_separate
to the TARGETs.
gcc/ChangeLog:
* shrink-wrap.cc (try_shrink_wrapping_separate):call
use_shrink_wrapping_separate.
(use_shrink_wrapping_separate): wrap the condition
check in
Generate cm.popretz instead of cm.popret if return value is 0.
gcc/ChangeLog:
* config/riscv/riscv.cc
(riscv_zcmp_can_use_popretz): true if popretz can be used
(riscv_gen_multi_pop_insn): interface to generate cm.pop[ret][z]
(riscv_expand_epilogue): expand
From: Die Li
Signed-off-by: Die Li
Co-Authored-By: Fei Gao
gcc/ChangeLog:
* config/riscv/peephole.md: New pattern.
* config/riscv/predicates.md (a0a1_reg_operand): New predicate.
(zcmp_mv_sreg_operand): New predicate.
* config/riscv/riscv.md: New predicate
define S10_MASK (1 << S10_REGNUM)
+#define S11_MASK (1 << S11_REGNUM)
+
+#define MULTI_PUSH_GPR_MASK
\
+ (RETURN_ADDR_MASK | S0_MASK | S1_MASK | S2_MASK | S3_MASK | S4_MASK
\
+ | S5_MASK | S6_MASK | S7_MASK | S8_MAS
Fei Gao (3):
[RISC-V] support cm.push cm.pop cm.popret in zcmp
[RISC-V] support cm.popretz in zcmp
[RISC-V] support cm.mva01s cm.mvsa01 in zcmp
gcc/config/riscv/iterators.md | 15 +
gcc/config/riscv/peephole.md | 28 +
gcc/config/riscv/predicates.md
On 2023-08-29 06:54 Jeff Law wrote:
>
>
>
>On 8/28/23 01:47, Fei Gao wrote:
>> no functional changes but allow targets to check shrink-wrap-separate
>> enabled or not.
>>
>> gcc/ChangeLog:
>>
>> * sh
onfirmed by you:
1. flag_shrink_wrap_separate seems better than flag_shrink_wrap.
2. to pass the zcmp testcases, i will add fno-shrink-wrap-separate option.
BR,
Fei
>
>On Mon, Aug 28, 2023 at 3:48 PM Fei Gao wrote:
>>
>> The first is a helper patch to allow targets to check
ttps://patchwork.sourceware.org/project/gcc/patch/20230607055215.29332-2-gao...@eswincomputing.com/
The rest of zcmp patches will be send out after the new series accepted to
avoid rebase again an again.
BR,
Fei
On 2023-08-20 18:53 Fei Gao wrote:
>
>
>Hi Kito
>
>This issue is due to zcmp and s
< S8_REGNUM)
+#define S9_MASK (1 << S9_REGNUM)
+#define S10_MASK (1 << S10_REGNUM)
+#define S11_MASK (1 << S11_REGNUM)
+
+#define MULTI_PUSH_GPR_MASK
\
+ (RETURN_ADDR_MASK | S0_MASK | S1_MASK | S2_MASK | S3_MASK | S4_MASK
The first is a helper patch to allow targets to check shrink-wrap-separate
enabled or not.
The second is zcmp extension implementation in RISC-V.
Fei Gao (2):
allow target to check shrink-wrap-separate enabled or not
support cm.push cm.pop cm.popret in zcmp and resolve confilct with
shrink
no functional changes but allow targets to check shrink-wrap-separate enabled
or not.
gcc/ChangeLog:
* shrink-wrap.cc (try_shrink_wrapping_separate):call
use_shrink_wrapping_separate.
(use_shrink_wrapping_separate): wrap the condition
check in
Hi Kito
This issue is due to zcmp and shrink-wrap-separate conflict,
which has been addressed by an under-review patch.
[PATCH 0/2] resolve confilct between RISC-V zcmp and shrink-wrap-separate
https://patchwork.sourceware.org/project/gcc/list/?series=21577
Hi Kito
Root cause has been identified.
Here's the frame layout fo the TC, please use courier font :)
+---+
| |
| GPR save area 112 B |
| |
Hi Kito
Thanks for reporting these 2 issues.
Let me check and feedback you soon.
BR
Fei
On 2023-08-16 16:38 Kito Cheng wrote:
>
>Another fail case for CFI:
>
>$ riscv64-unknown-elf-gcc _mulhc3.i
>-march=rv64imafd_zicsr_zifencei_zca_zcmp -mabi=lp64d -g -O2 -o
>_mulhc3.s
>
>typedef float a
hi Jeff
Please see my earlier reply here.
https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg310656.html
Maybe you scrolled past it in so many emails:)
BR,
Fei
On 2023-06-25 21:36 Jeff Law wrote:
>
>
>
>On 6/20/23 03:40, Fei Gao wrote:
>> gcc/ChangeLog:
>>
>
gcc/ChangeLog:
* shrink-wrap.cc (try_shrink_wrapping_separate):call
use_shrink_wrapping_separate.
(use_shrink_wrapping_separate): wrap the condition
check in use_shrink_wrapping_separate.
* shrink-wrap.h (use_shrink_wrapping_separate): add to extern
---
These 2 patches resolve confilct between zcmp multi push/pop and
shrink-wrap-separate.
As per Kito's review comment
https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg310564.html,
I split the orginal patch into two parts: RISC-V part and
the rest part (shrink-wrap.h / shrink-wrap.cc).
Fei
:
...
sw s1,20(sp)
sw s3,12(sp)
...
sw s2,16(sp)
Signed-off-by: Fei Gao
Co-Authored-By: Zhangjin Liao
gcc/ChangeLog:
* config/riscv/riscv.cc
(riscv_avoid_shrink_wrapping_separate): wrap the condition check
On 2023-06-13 03:26 Jeff Law wrote:
>
>
>
>On 6/6/23 23:52, Fei Gao wrote:
>> Disable zcmp multi push/pop if shrink-wrap-separate is active.
>>
>> So in -Os that prefers smaller code size, by default shrink-wrap-separate
>> is disabled while zcmp multi p
-by: Fei Gao
Co-Authored-By: Zhangjin Liao
---
gcc/config/riscv/riscv.cc | 19 +++-
gcc/shrink-wrap.cc| 25 +++--
gcc/shrink-wrap.h | 1 +
.../riscv/zcmp_shrink_wrap_separate.c | 97 +++
.../riscv
From: Die Li
Signed-off-by: Die Li
Co-Authored-By: Fei Gao
gcc/ChangeLog:
* config/riscv/peephole.md: New pattern.
* config/riscv/predicates.md (a0a1_reg_operand): New predicate.
(zcmp_mv_sreg_operand): New predicate.
* config/riscv/riscv.md: New predicate
Zcmp can share the same logic as save-restore in stack allocation:
pre-allocation
by cm.push, step 1 and step 2.
please be noted cm.push pushes ra, s0-s11 in reverse order than what
save-restore does.
So adaption has been done in .cfi directives in my patch.
Signed-off-by: Fei Gao
gcc
Generate cm.popretz instead of cm.popret if return value is 0.
Signed-off-by: Fei Gao
gcc/ChangeLog:
* config/riscv/riscv.cc
(riscv_zcmp_can_use_popretz): true if popretz can be used
(riscv_gen_multi_pop_insn): interface to generate cm.pop[ret][z
please be noted the series depend on the zcmp switch that Jiawei posted
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/615289.html
The 1st patch is a follow up on Kito's V3 review.
Others are new.
Fei Gao (4):
[RISC-V] support cm.push cm.pop cm.popret in zcmp
[RISC-V] support
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_adjust_libcall_cfi_prologue): use Pmode
for cfi reg/mem machmode
(riscv_adjust_libcall_cfi_epilogue): use Pmode for cfi reg machmode
gcc/testsuite/ChangeLog:
* gcc.target/riscv/save-restore-cfi-2.c: New test to check
mp can share the same logic as save-restore in stack allocation:
>> pre-allocation
>> by cm.push, step 1 and step 2.
>>
>> please be noted cm.push pushes ra, s0-s11 in reverse order than what
>> save-restore does.
>> So adaption has been done in .cfi direct
gcc/testsuite/ChangeLog:
* gcc.target/riscv/save-restore-cfi.c: New test to check save-restore
cfi directives.
---
.../gcc.target/riscv/save-restore-cfi.c | 17 +
1 file changed, 17 insertions(+)
create mode 100644
Zcmp can share the same logic as save-restore in stack allocation:
pre-allocation
by cm.push, step 1 and step 2.
please be noted cm.push pushes ra, s0-s11 in reverse order than what
save-restore does.
So adaption has been done in .cfi directives in my patch.
Signed-off-by: Fei Gao
gcc
This patch fixes a cfi issue introduced by
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=60524be1e3929d83e15fceac6e2aa053c8a6fb20
Test code:
char my_getchar();
float getf();
int test_f0()
{
int s0 = my_getchar();
float f0 = getf();
int b = my_getchar();
return f0+s0+b;
}
cflags: -g -Os
On 2023-05-31 18:13 Kito Cheng wrote:
>
>> >[1]
>> >https://patchwork.sourceware.org/project/gcc/patch/20230406062118.47431-5-jia...@iscas.ac.cn/
>> Thanks for your review.
>>
>> The md file looks verbose with bunch of *_offset_operand and
>> stack_push_up_to_*_operand, but it significantly
>>
(use_restore_libcall || use_multi_pop)
> frame->mask = 0; /* Temporarily fib that we need not save GPRs. */
> /* Restore the registers. */
>- riscv_for_each_saved_reg (frame->total_size - step2 - libcall_size,
>+ riscv_for_each_saved_reg (frame->total_size - step2 - libcall_size -
On 2023-05-29 11:05 Kito Cheng wrote:
>
>Thanks for this patch, just few minor comment, I think this is pretty
>close to accept :)
>
>Could you reference JiaWei's match_parallel[1] to prevent adding bunch
>of *_offset_operand and stack_push_up_to_*_operand?
>
>
>[1]
On 2023-05-12 16:12 Sinan wrote:
>
>Hi Fei,
>Sorry for the late reply, I've been busy with moving these days :(.
>Thanks for working on it. I would prefer removing the extra pass for popretz
>if possible ... I will test your patches ASAP.
>BR,
>Sinan
hi Sinan
I posted V2 based on Kito's
e S6_MASK ( 1 << S6_REGNUM)
+#define S7_MASK ( 1 << S7_REGNUM)
+#define S8_MASK ( 1 << S8_REGNUM)
+#define S9_MASK ( 1 << S9_REGNUM)
+#define S10_MASK( 1 << S10_REGNUM)
+#define S11_MA
them in my patch series.
Please pick up Jiawei's [PATCH 1/5] before picking up my patch series.
Fei Gao (1):
[RISC-V] support cm.push cm.pop cm.popret in zcmp
gcc/config/riscv/predicates.md| 148 +++
gcc/config/riscv/riscv-protos.h |2 +
gcc/config/riscv
On 2023-05-08 10:48 Kito Cheng wrote:
>
>diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md
>new file mode 100644
>index 000..1c2f390269e
>--- /dev/null
>+++ b/gcc/config/riscv/zc.md
>@@ -0,0 +1,55 @@
>...
>+(define_insn "gpr_multi_pop"
>+ [(unspec_volatile [(match_operand 0
fast or -Os/-Oz.
>
I see and fully agree.
I'll find a better way to resolve the conflict,
My current idea is to diasble zcmp when shrink-wrap-separate is actually
active.
Thanks Kito and Andrew Pinski for your patience.
BR,
Fei
>On Mon, May 8, 2023 at 4:54 PM Fei Gao wrote:
>>
&
On 2023-05-08 16:05 Kito Cheng wrote:
>
>> > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
>> > index 45a63cab9c9..629e5e45cac 100644
>> > --- a/gcc/config/riscv/riscv.cc
>> > +++ b/gcc/config/riscv/riscv.cc
>> > @@ -5729,7 +5729,8 @@ riscv_get_separate_components (void)
>>
or delete.
BR,
Fei
>On Sat, May 6, 2023 at 4:41 PM Fei Gao wrote:
>>
>> zcmp aims to reduce code size, while shrink-wrap-separate prefers
>> speed to code size. So disable shrink-wrap-separate if zcmp
>> enabled, just like what save-restore has done.
>>
>>
On 2023-05-05 23:57 Sinan wrote:
>
>> hi Jiawei
>>
>> Please ignore my previous reply. I accidently sent the email before I
>> finished it.
>> Sorry for that!
>>
>> I downloaded the series of patches from you and found in some cases
>> it fails to generate zcmp push and pop insns.
>>
>> TC:
>>
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