On Fri, Sep 10, 2021 at 6:54 PM Richard Biener
wrote:
>
> On Fri, Sep 10, 2021 at 5:03 AM Hongtao Liu wrote:
> >
> > On Fri, Sep 10, 2021 at 7:49 AM Segher Boessenkool
> > wrote:
> > >
> > > On Thu, Sep 09, 2021 at 08:16:16AM +0200, Richard Biener wrote
On Thu, Jul 1, 2021 at 2:17 PM liuhongt wrote:
>
> From: "H.J. Lu"
>
> gcc/ChangeLog:
>
> * config/i386/i386-expand.c
> (ix86_avx256_split_vector_move_misalign): Handle V16HF mode.
> * config/i386/i386.c
> (ix86_preferred_simd_mode): Handle HF mode.
> *
On Thu, Sep 9, 2021 at 4:00 PM Hongtao Liu wrote:
>
> On Thu, Sep 9, 2021 at 3:54 PM liuhongt wrote:
> >
> > Hi:
> > As a follow up of [1], the patch removes all scalar mode copysign related
> > post_reload splitter/define_insn and expand copysign directly into be
On Fri, Sep 10, 2021 at 7:49 AM Segher Boessenkool
wrote:
>
> On Thu, Sep 09, 2021 at 08:16:16AM +0200, Richard Biener wrote:
> > > I think we should (longer term) get rid of the overloaded meanings and
> > > uses of subregs. One fairly simple thing is to make a new rtx code
> > > "bit_cast" (or
On Thu, Sep 9, 2021 at 11:31 PM H.J. Lu wrote:
>
> On Wed, Jul 21, 2021 at 12:44 AM liuhongt wrote:
> >
> > From: "H.J. Lu"
> >
> > Copied from regular XMM ABI tests. Only run AVX512FP16 ABI tests for ELF
> > targets.
> >
> > gcc/testsuite/ChangeLog:
> >
> > *
On Thu, Sep 9, 2021 at 3:54 PM liuhongt wrote:
>
> Hi:
> As a follow up of [1], the patch removes all scalar mode copysign related
> post_reload splitter/define_insn and expand copysign directly into below using
> paradoxical subregs.
[1]
On Thu, Jul 1, 2021 at 2:17 PM liuhongt wrote:
>
> gcc/ChangeLog:
>
> * config.gcc: Add avx512fp16vlintrin.h.
> * config/i386/avx512fp16intrin.h: (_mm512_add_ph): New intrinsic.
> (_mm512_mask_add_ph): Likewise.
> (_mm512_maskz_add_ph): Likewise.
>
On Thu, Sep 9, 2021 at 11:21 AM H.J. Lu via Gcc-patches
wrote:
>
> 1. Add TARGET_AVX256_MOVE_BY_PIECES to perform move by-pieces operation
> with 256-bit AVX instructions.
> 2. Add TARGET_AVX256_STORE_BY_PIECES to perform move and store by-pieces
> operations with 256-bit AVX instructions.
>
>
On Thu, Sep 9, 2021 at 3:17 AM Segher Boessenkool
wrote:
>
> On Wed, Sep 08, 2021 at 08:39:31PM +0200, Richard Biener wrote:
> > On September 8, 2021 7:08:09 PM GMT+02:00, Segher Boessenkool
> > wrote:
> > >It is not a good idea to do allow all those things. Most backends can
> > >only support
On Thu, Sep 9, 2021 at 3:17 AM Segher Boessenkool
wrote:
>
> On Wed, Sep 08, 2021 at 08:39:31PM +0200, Richard Biener wrote:
> > On September 8, 2021 7:08:09 PM GMT+02:00, Segher Boessenkool
> > wrote:
> > >It is not a good idea to do allow all those things. Most backends can
> > >only support
On Wed, Sep 8, 2021 at 6:02 PM Jakub Jelinek wrote:
>
> On Wed, Sep 08, 2021 at 06:00:50PM +0800, Hongtao Liu wrote:
> > Yes, I think so.
> > And I find paradoxical subreg like (subreg:V4SF (reg:SF)) are not
> > allowed by validate_subreg until r11-621.
> > T
On Wed, Sep 8, 2021 at 5:33 PM Jakub Jelinek wrote:
>
> On Wed, Sep 08, 2021 at 05:23:40PM +0800, Hongtao Liu wrote:
> > > Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
> > >
> > Patch LGTM.
>
> Thanks, committed.
>
> > PS:
&
On Wed, Sep 8, 2021 at 5:09 PM Jakub Jelinek wrote:
>
> On Wed, Sep 08, 2021 at 10:37:17AM +0800, Hongtao Liu wrote:
> > Bootstrapped and regtested on x86_64-linux-gnu{-m32,}.
> > Ok for trunk?
> >
> > libgcc/ChangeLog:
> >
> > * co
On Wed, Sep 8, 2021 at 3:43 PM Jakub Jelinek via Gcc-patches
wrote:
>
> Hi!
>
> As the testcase shows, we miscompile @xorsign3_1 if both input
> operands are in the same register, because the splitter overwrites op1
> before with op1 & mask before using op0.
>
> For dest = xorsign op0, op0 we can
On Wed, Sep 8, 2021 at 10:54 AM Hongtao Liu wrote:
>
> On Wed, Jul 21, 2021 at 3:43 PM liuhongt wrote:
> >
> > Hi:
> > As discussed in [1], this patch support _Float16 under target sse2
> > and above, w/o avx512fp16, _Float16 type is storage only, all operatio
On Wed, Jul 21, 2021 at 3:43 PM liuhongt wrote:
>
> Hi:
> As discussed in [1], this patch support _Float16 under target sse2
> and above, w/o avx512fp16, _Float16 type is storage only, all operations
> are emulated by soft-fp and float instructions. Soft-fp keeps the intermediate
> result of
On Wed, Sep 8, 2021 at 8:54 AM Hongtao Liu wrote:
>
> On Tue, Sep 7, 2021 at 8:29 PM Jakub Jelinek via Gcc-patches
> wrote:
> >
> > On Mon, Sep 06, 2021 at 10:58:53AM +0200, Jakub Jelinek via Gcc-patches
> > wrote:
> > > On Mon, Sep 06, 2021 at 08:49:27AM +0
On Wed, Sep 8, 2021 at 7:20 AM Segher Boessenkool
wrote:
>
> On Fri, Sep 03, 2021 at 05:05:47PM +0200, Andreas Schwab wrote:
> > On Sep 02 2021, Segher Boessenkool wrote:
> > > On Tue, Aug 31, 2021 at 07:17:49PM +0800, liuhongt via Gcc-patches wrote:
> > >>* emit-rtl.c (validate_subreg): Get
On Tue, Sep 7, 2021 at 8:29 PM Jakub Jelinek via Gcc-patches
wrote:
>
> On Mon, Sep 06, 2021 at 10:58:53AM +0200, Jakub Jelinek via Gcc-patches wrote:
> > On Mon, Sep 06, 2021 at 08:49:27AM +0100, Iain Sandoe wrote:
> > > > Ok. The *.ver changes are still needed (see above), but that can be
> >
On Tue, Sep 7, 2021 at 3:18 PM Jakub Jelinek wrote:
>
> On Tue, Sep 07, 2021 at 09:52:57AM +0800, Hongtao Liu wrote:
> > Adjust the wording for x86 _Float16 type.
> >
> > gcc/ChangeLog:
> >
> > * doc/extend.texi: (@node Floating Types): Adjust the wordin
On Tue, Sep 7, 2021 at 12:37 AM Joseph Myers wrote:
>
> On Mon, 6 Sep 2021, liuhongt via Gcc-patches wrote:
>
> > Hi:
> > As discussed in [1], most of (currently unopposed) targets want
> > auto-vectorization at O2, and IMHO now would be a good time to enable O2
> > vectorization for GCC trunk,
On Mon, Sep 6, 2021 at 8:13 PM Jakub Jelinek wrote:
>
> On Mon, Sep 06, 2021 at 10:05:00AM +0800, Hongtao Liu wrote:
>
> > @@ -1076,9 +1076,11 @@ systems where @code{__float128} is supported.
> > The @code{_Float32}
> > type is supported on all systems supporting IE
On Mon, Sep 6, 2021 at 8:35 PM H.J. Lu wrote:
>
> On Sun, Sep 5, 2021 at 10:34 PM Hongtao Liu wrote:
> >
> > On Sun, Sep 5, 2021 at 5:56 AM H.J. Lu via Gcc-patches
> > wrote:
> > >
> > > Enable FMA in scalar/vector unsigned SI to SF expanders.
>
On Mon, Sep 6, 2021 at 7:01 PM Jakub Jelinek wrote:
>
> On Mon, Sep 06, 2021 at 06:58:37PM +0800, Hongtao Liu wrote:
> > > process_options would mean it affects only the command line and not
> > > __attribute__((optimize ("O2", "ftree-vectorize")))
On Mon, Sep 6, 2021 at 5:42 PM Jakub Jelinek via Gcc-patches
wrote:
>
> On Mon, Sep 06, 2021 at 11:18:47AM +0200, Richard Biener wrote:
> > On Mon, Sep 6, 2021 at 10:47 AM liuhongt via Gcc-patches
> > wrote:
> > >
> > > Hi:
> > > As discussed in [1], most of (currently unopposed) targets want
On Mon, Sep 6, 2021 at 6:03 PM Richard Biener via Gcc-patches
wrote:
>
> On Mon, 6 Sep 2021, liuhongt wrote:
>
> > Hi:
> > For the conversion from _Float16 to int, if the corresponding optab
> > does not exist, the compiler will try the wider mode (SFmode here),
> > but when floatsfsi exists
On Mon, Sep 6, 2021 at 5:19 PM Richard Biener via Gcc-patches
wrote:
>
> On Mon, Sep 6, 2021 at 10:47 AM liuhongt via Gcc-patches
> wrote:
> >
> > Hi:
> > As discussed in [1], most of (currently unopposed) targets want
> > auto-vectorization at O2, and IMHO now would be a good time to enable
On Mon, Sep 6, 2021 at 2:54 PM Richard Biener
wrote:
>
> On Thu, Sep 2, 2021 at 7:54 PM Richard Sandiford
> wrote:
> >
> > Hongtao Liu via Gcc-patches writes:
> > > On Wed, Sep 1, 2021 at 8:52 PM Richard Sandiford
> > > wrote:
> > >>
> >
On Mon, Sep 6, 2021 at 4:46 PM liuhongt via Gcc-patches
wrote:
>
> Hi:
> As discussed in [1], most of (currently unopposed) targets want
> auto-vectorization at O2, and IMHO now would be a good time to enable O2
> vectorization for GCC trunk, so it would leave enough time to expose
> related
On Sun, Sep 5, 2021 at 5:56 AM H.J. Lu via Gcc-patches
wrote:
>
> Enable FMA in scalar/vector unsigned SI to SF expanders.
>
> gcc/
>
> PR target/85819
> * config/i386/i386-expand.c (ix86_expand_convert_uns_sisf_sse):
> Enable FMA.
>
On Sun, Sep 5, 2021 at 5:54 AM H.J. Lu via Gcc-patches
wrote:
>
> Add non-destructive source alternative to @xorsign3_1 for AVX.
LGTM.
>
> gcc/
>
> PR target/89984
> * config/i386/i386-expand.c (ix86_split_xorsign): Use operands[2].
> * config/i386/i386.md (@xorsign3_1):
On Fri, Sep 3, 2021 at 8:42 PM Jakub Jelinek via Gcc-patches
wrote:
>
> On Mon, Aug 02, 2021 at 02:31:12PM +0800, liuhongt via Gcc-patches wrote:
> > * doc/extend.texi (Half-Precision Floating Point): Documemt
> > _Float16 for x86.
>
> > --- a/gcc/doc/extend.texi
> > +++
On Fri, Sep 3, 2021 at 5:01 PM Jakub Jelinek via Gcc-patches
wrote:
>
> On Fri, Sep 03, 2021 at 03:41:13PM +0800, liuhongt via Gcc-patches wrote:
> > --- a/libgcc/config/i386/64/t-softfp
> > +++ b/libgcc/config/i386/64/t-softfp
> > @@ -1 +1,6 @@
> > softfp_extras := fixhfti fixunshfti floattihf
On Fri, Sep 3, 2021 at 5:01 PM Jakub Jelinek via Gcc-patches
wrote:
>
> On Fri, Sep 03, 2021 at 03:41:13PM +0800, liuhongt via Gcc-patches wrote:
> > --- a/libgcc/config/i386/64/t-softfp
> > +++ b/libgcc/config/i386/64/t-softfp
> > @@ -1 +1,6 @@
> > softfp_extras := fixhfti fixunshfti floattihf
On Thursday, September 2, 2021, H.J. Lu wrote:
> On Wed, Sep 1, 2021 at 11:00 PM Hongtao Liu wrote:
> >
> > I'm going to check in the first 3 patches which are already approved.
> >
> > Update hf soft-fp from glibc.
> > [i386] Enable _Float16 type for T
On Thursday, September 2, 2021, Iain Sandoe wrote:
> Hi Hongtao.
>
> > On 2 Sep 2021, at 07:06, Hongtao Liu via Gcc-patches <
> gcc-patches@gcc.gnu.org> wrote:
> >
> > I'm going to check in the first 3 patches which are already approved.
> >
> > Upd
On Wed, Sep 1, 2021 at 8:52 PM Richard Sandiford
wrote:
>
> Richard Biener writes:
> > On Wed, Sep 1, 2021 at 8:28 AM Hongtao Liu wrote:
> >>
> >> On Tue, Aug 31, 2021 at 7:56 PM Richard Biener
> >> wrote:
> >> >
> &g
On Tue, Aug 24, 2021 at 5:39 PM Hongtao Liu wrote:
>
> On Tue, Aug 17, 2021 at 9:53 AM Hongtao Liu wrote:
> >
> > On Fri, Aug 6, 2021 at 2:06 PM Hongtao Liu wrote:
> > >
> > > On Tue, Aug 3, 2021 at 10:44 AM Hongtao Liu wrote:
> > > >
>
I'm going to check in the first 3 patches which are already approved.
Update hf soft-fp from glibc.
[i386] Enable _Float16 type for TARGET_SSE2 and above.
[i386] libgcc: Enable hfmode soft-sf/df/xf/tf extensions and
truncations.
On Mon, Aug 2, 2021 at 2:31 PM liuhongt wrote:
>
>
On Tue, Aug 31, 2021 at 7:56 PM Richard Biener
wrote:
>
> On Tue, Aug 31, 2021 at 12:18 PM Hongtao Liu wrote:
> >
> > On Mon, Aug 30, 2021 at 8:25 PM Richard Biener via Gcc-patches
> > wrote:
> > >
> > > On Fri, Aug 27, 2021 at 8:53 AM liuh
On Mon, Aug 30, 2021 at 8:25 PM Richard Biener via Gcc-patches
wrote:
>
> On Fri, Aug 27, 2021 at 8:53 AM liuhongt wrote:
> >
> > When gimple simplifcation try to combine op and vec_cond_expr to cond_op,
> > it doesn't check if mask type matches. It causes an ICE when expand cond_op
> > with
On Tue, Aug 31, 2021 at 2:30 PM Hongtao Liu wrote:
>
> On Tue, Aug 31, 2021 at 2:11 PM Richard Biener
> wrote:
> >
> > On Fri, Aug 27, 2021 at 6:50 AM Hongtao Liu wrote:
> > >
> > > On Thu, Aug 26, 2021 at 7:09 PM Richard Biener via Gcc-patches
> > &
On Tue, Aug 31, 2021 at 2:11 PM Richard Biener
wrote:
>
> On Fri, Aug 27, 2021 at 6:50 AM Hongtao Liu wrote:
> >
> > On Thu, Aug 26, 2021 at 7:09 PM Richard Biener via Gcc-patches
> > wrote:
> > >
> > > On Thu, Aug 26, 2021 at 12:50 PM Richard Sandi
On Fri, Aug 27, 2021 at 10:03 AM Kong, Lingling via Gcc-patches
wrote:
>
> Hi,
>
> For avx512f_scattersi, mask operand only affect set src, we need
> to refine the pattern to let gcc know mask register also affect the dest.
> So we put mask operand into UNSPEC_VSIBADDR.
>
> Bootstrapped and
On Thu, Aug 26, 2021 at 7:09 PM Richard Biener via Gcc-patches
wrote:
>
> On Thu, Aug 26, 2021 at 12:50 PM Richard Sandiford
> wrote:
> >
> > Richard Biener via Gcc-patches writes:
> > > On Thu, Aug 26, 2021 at 11:06 AM Richard Sandiford
> > > wrote:
> > >>
> > >> Richard Biener via
On Thu, Aug 26, 2021 at 12:57 PM liuhongt wrote:
>
> This patch is a follow-up to [1], it fold all shufps/shufpd builtins into
> gimple.
Of course for non-mask or mask all-ones version.
> Bootstrapped and regtested on x86_64-linux-gnu{-m32,}.
>
> [1]
On Thu, Aug 26, 2021 at 7:16 AM Jeff Law wrote:
>
>
>
> On 8/24/2021 3:44 AM, Hongtao Liu via Gcc-patches wrote:
>
> On Tue, Aug 24, 2021 at 5:40 PM Hongtao Liu wrote:
>
> On Tue, Aug 17, 2021 at 9:52 AM Hongtao Liu wrote:
>
> On Mon, Aug 9, 2021 at 4:34 PM Hongtao
On Tue, Aug 24, 2021 at 7:39 PM Richard Biener
wrote:
>
> On Tue, Aug 24, 2021 at 11:38 AM Hongtao Liu wrote:
> >
> > On Tue, Aug 24, 2021 at 5:40 PM Hongtao Liu wrote:
> > >
> > > On Tue, Aug 17, 2021 at 9:52 AM Hongtao Liu wrote:
> > > >
&g
On Wed, Aug 25, 2021 at 5:14 AM Segher Boessenkool
wrote:
>
> Hi!
>
> On Tue, Aug 24, 2021 at 04:55:30PM +0800, liuhongt wrote:
> > This patch extend change_zero_ext to change illegitimate constant
> > into constant pool, this will enable simplification of below:
>
> It should be in a separate
On Wed, Aug 25, 2021 at 5:14 AM Segher Boessenkool
wrote:
>
> Hi!
>
> On Tue, Aug 24, 2021 at 04:55:30PM +0800, liuhongt wrote:
> > This patch extend change_zero_ext to change illegitimate constant
> > into constant pool, this will enable simplification of below:
>
> It should be in a separate
On Wed, Aug 25, 2021 at 2:14 PM Kong, Lingling via Gcc-patches
wrote:
>
> Hi,
>
> For avx512f_scattersi, mask operand only affect set src, we
> need to refine the pattern to let gcc know mask register also affect the dest.
> So we put mask operand into UNSPEC_VSIBADDR.
>
> Bootstrapped and
On Tue, Aug 24, 2021 at 9:11 PM Bernhard Reutner-Fischer
wrote:
>
> On Tue, 24 Aug 2021 17:53:27 +0800
> Hongtao Liu via Gcc-patches wrote:
>
> > On Tue, Aug 24, 2021 at 9:36 AM liuhongt wrote:
> > >
> > > Also optimize below 3 forms to vpternlog, op1,
On Tue, Aug 24, 2021 at 6:25 PM liuhongt wrote:
>
> gcc/ChangeLog:
>
> PR target/101989
> * config/i386/sse.md (_vternlog):
> Enable avx512 embedded broadcast.
> (*_vternlog_all): Ditto.
> (_vternlog_mask): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> PR
On Tue, Aug 24, 2021 at 9:36 AM liuhongt wrote:
>
> Also optimize below 3 forms to vpternlog, op1, op2, op3 are
> register_operand or unary_p as (not reg)
>
> A: (any_logic (any_logic op1 op2) op3)
> B: (any_logic (any_logic op1 op2) (any_logic op3 op4)) op3/op4 should
> be equal to op1/op2
> C:
On Tue, Aug 24, 2021 at 5:40 PM Hongtao Liu wrote:
>
> On Tue, Aug 17, 2021 at 9:52 AM Hongtao Liu wrote:
> >
> > On Mon, Aug 9, 2021 at 4:34 PM Hongtao Liu wrote:
> > >
> > > On Fri, Aug 6, 2021 at 7:27 PM Richard Biener via Gcc-patches
> > > wro
On Tue, Aug 17, 2021 at 9:52 AM Hongtao Liu wrote:
>
> On Mon, Aug 9, 2021 at 4:34 PM Hongtao Liu wrote:
> >
> > On Fri, Aug 6, 2021 at 7:27 PM Richard Biener via Gcc-patches
> > wrote:
> > >
> > > On Fri, Aug 6, 2021 at 11:05 AM Richard Sandiford
&g
On Tue, Aug 17, 2021 at 9:53 AM Hongtao Liu wrote:
>
> On Fri, Aug 6, 2021 at 2:06 PM Hongtao Liu wrote:
> >
> > On Tue, Aug 3, 2021 at 10:44 AM Hongtao Liu wrote:
> > >
> > > On Tue, Aug 3, 2021 at 3:34 AM Joseph Myers
> > > wrote:
> > >
On Tue, Aug 24, 2021 at 9:43 AM H.J. Lu wrote:
>
> On Mon, Aug 23, 2021 at 6:17 PM Hongtao Liu wrote:
> >
> > On Tue, Aug 24, 2021 at 9:01 AM H.J. Lu via Gcc-patches
> > wrote:
> > >
> > > Broadcast from integer to a pseudo vector register instead of
On Mon, Aug 23, 2021 at 9:14 PM H.J. Lu wrote:
>
> On Mon, Aug 23, 2021 at 03:23:26PM +0800, Hongtao Liu wrote:
> > On Sun, Aug 22, 2021 at 8:54 PM H.J. Lu via Gcc-patches
> > wrote:
> > >
> > > In vetor move pattern, repla
On Tue, Aug 24, 2021 at 9:01 AM H.J. Lu via Gcc-patches
wrote:
>
> Broadcast from integer to a pseudo vector register instead of a hard
> vector register to allow LRA to remove redundant move instruction after
> broadcast.
>
> gcc/
>
> PR target/102021
> *
On Sun, Aug 22, 2021 at 8:54 PM H.J. Lu via Gcc-patches
wrote:
>
> In vetor move pattern, replace nonimmediate_or_sse_const_operand with
> nonimmediate_or_sse_const_vector_operand to allow vector load from
> non-uniform CONST_VECTOR. Non-uniform CONST_VECTOR is enabled only in
> the combine pass
On Wed, Aug 18, 2021 at 7:37 PM Hongtao Liu wrote:
>
> On Wed, Aug 18, 2021 at 7:30 PM Hongtao Liu wrote:
> >
> > On Wed, Aug 18, 2021 at 6:28 PM Richard Biener wrote:
> > >
> > > On Wed, 18 Aug 2021, Richard Biener wrote:
> > >
> > > &g
On Wed, Aug 18, 2021 at 7:30 PM Hongtao Liu wrote:
>
> On Wed, Aug 18, 2021 at 6:28 PM Richard Biener wrote:
> >
> > On Wed, 18 Aug 2021, Richard Biener wrote:
> >
> > >
> > > So in the end I seem to be able to combine AVX & AVX512 arriving
> &g
On Wed, Aug 18, 2021 at 6:28 PM Richard Biener wrote:
>
> On Wed, 18 Aug 2021, Richard Biener wrote:
>
> >
> > So in the end I seem to be able to combine AVX & AVX512 arriving
> > at the following which passes basic testing. I will now see to
> > teach the vectorizer the required "promotion" to
On Wed, Aug 18, 2021 at 5:54 PM Richard Biener wrote:
>
>
> So in the end I seem to be able to combine AVX & AVX512 arriving
> at the following which passes basic testing. I will now see to
> teach the vectorizer the required "promotion" to handle
> mask_gather_loadv4dfv4si and
On Wed, Aug 18, 2021 at 4:32 PM Richard Biener wrote:
>
> On Wed, 18 Aug 2021, Hongtao Liu wrote:
>
> > On Wed, Aug 18, 2021 at 11:24 AM Hongtao Liu wrote:
> > >
> > > On Tue, Aug 17, 2021 at 10:43 PM Richard Biener via Gcc-patches
> > > wrote:
>
On Tue, Aug 17, 2021 at 5:06 PM liuhongt wrote:
>
> Hi:
> This patch add a new x86 tune named X86_TUNE_V2DF_REDUCTION_PREFER_HADDPD
> to enable haddpd for v2df vector reduction, the tune is disabled by default.
>
> Bootstrapped and regtested on x86_64-linux-gnu{-m32,}
> Ok for trunk?
>
On Wed, Aug 18, 2021 at 11:24 AM Hongtao Liu wrote:
>
> On Tue, Aug 17, 2021 at 10:43 PM Richard Biener via Gcc-patches
> wrote:
> >
> > On Tue, Aug 17, 2021 at 3:29 PM Richard Biener via Gcc-patches
> > wrote:
> > >
> > > This is an attempt to start
On Tue, Aug 17, 2021 at 10:43 PM Richard Biener via Gcc-patches
wrote:
>
> On Tue, Aug 17, 2021 at 3:29 PM Richard Biener via Gcc-patches
> wrote:
> >
> > This is an attempt to start moving the x86 backend to use
> > standard pattern names for [mask_]gather_load and [mask_]scatter_store
> >
On Tue, Aug 17, 2021 at 10:43 PM Richard Biener via Gcc-patches
wrote:
>
> On Tue, Aug 17, 2021 at 3:29 PM Richard Biener via Gcc-patches
> wrote:
> >
> > This is an attempt to start moving the x86 backend to use
> > standard pattern names for [mask_]gather_load and [mask_]scatter_store
> >
On Tue, Aug 17, 2021 at 8:56 PM H.J. Lu via Gcc-patches
wrote:
>
> On Tue, Aug 17, 2021 at 5:43 AM liuhongt via Gcc-patches
> wrote:
> >
> > This reverts commit 872da9a6f664a06d73c987aa0cb2e5b830158a10.
> >
> > PR target/101936
> > PR target/101929
> >
> > Bootstrapped and regtested on
On Fri, Aug 6, 2021 at 2:06 PM Hongtao Liu wrote:
>
> On Tue, Aug 3, 2021 at 10:44 AM Hongtao Liu wrote:
> >
> > On Tue, Aug 3, 2021 at 3:34 AM Joseph Myers wrote:
> > >
> > > On Mon, 2 Aug 2021, liuhongt via Gcc-patches wrote:
> > >
> > > &
On Mon, Aug 9, 2021 at 4:34 PM Hongtao Liu wrote:
>
> On Fri, Aug 6, 2021 at 7:27 PM Richard Biener via Gcc-patches
> wrote:
> >
> > On Fri, Aug 6, 2021 at 11:05 AM Richard Sandiford
> > wrote:
> > >
> > > Richard Biener via Gcc-patches writes:
&g
On Mon, Aug 16, 2021 at 3:25 PM Hongtao Liu wrote:
>
> On Mon, Aug 16, 2021 at 3:11 PM Jakub Jelinek via Gcc-patches
> wrote:
> >
> > On Mon, Aug 16, 2021 at 01:18:38PM +0800, liuhongt via Gcc-patches wrote:
> > > + /* Accept VNxHImode and VNxQImode now. */
On Mon, Aug 16, 2021 at 3:11 PM Jakub Jelinek via Gcc-patches
wrote:
>
> On Mon, Aug 16, 2021 at 01:18:38PM +0800, liuhongt via Gcc-patches wrote:
> > + /* Accept VNxHImode and VNxQImode now. */
> > + if (!TARGET_AVX512VL && GET_MODE_SIZE (mode) < 64)
> > +return false;
> > +
> > + /*
On Thu, Aug 12, 2021 at 5:23 PM Jakub Jelinek wrote:
>
> On Thu, Aug 12, 2021 at 01:43:23PM +0800, liuhongt wrote:
> > Hi:
> > This is another patch to optimize vec_perm_expr to match vpmov{dw,dq,wb}
> > under AVX512.
> > For scenarios(like pr101846-2.c) where the upper half is not used, this
On Thu, Aug 12, 2021 at 3:49 PM Jakub Jelinek wrote:
>
> Hi!
>
> My patch from yesterday apparently broke some V32HImode permutations
> as the testcase shows.
> The first function assumed it would never be called in d->testing_p mode
> and so went right away into emitting the code.
> And the
On Thu, Aug 12, 2021 at 12:05 PM liuhongt wrote:
>
> Hi:
> This is the patch i'm going to checkin.
> Bootstrapped and regtested on x86_64-linux-gnu{-m32,};
>
>
> 2021-08-12 Uros Bizjak
>
> gcc/ChangeLog:
>
> PR target/98309
> * config/i386/i386.md (avx512f_scalef2): New
>
On Wed, Aug 11, 2021 at 7:16 PM Uros Bizjak wrote:
>
> On Wed, Aug 11, 2021 at 8:36 AM Uros Bizjak wrote:
> >
> > On Tue, Aug 10, 2021 at 2:13 PM liuhongt wrote:
> > >
> > > Hi:
> > > AVX512F supported vscalefs{s,d} which is the same as ldexp except the
> > > second operand should be
On Wed, Aug 11, 2021 at 3:58 PM Jakub Jelinek wrote:
>
> On Wed, Aug 11, 2021 at 02:43:06PM +0800, liuhongt wrote:
> > Add define_insn_and_split to combine avx_vec_concatv16si/2 and
> > avx512f_zero_extendv16hiv16si2_1 since the latter already zero_extend
> > the upper bits, similar for other
On Tue, Aug 10, 2021 at 4:54 PM Jakub Jelinek wrote:
>
> Hi!
>
> When working on the PR, I've noticed we generate terrible code for
> V32HImode or V64QImode permutations for -mavx512f -mno-avx512bw.
> Generally we can't do much with such permutations, but since PR68655
> we can handle at least
On Tue, Aug 10, 2021 at 4:44 PM Jakub Jelinek wrote:
>
> Hi!
>
> On the following testcase we emit
> vmovdqa32 .LC0(%rip), %zmm1
> vpermd %zmm0, %zmm1, %zmm0
> and
> vmovdqa64 .LC1(%rip), %zmm1
> vpermq %zmm0, %zmm1, %zmm0
> instead of
>
On Tue, Aug 10, 2021 at 4:11 PM Hongyu Wang via Gcc-patches
wrote:
>
> Hi,
>
> This patch fixes some typo in amxbf16-dpbf16ps-2 test.
>
> Tested under sde/spr machine and passed.
>
> OK for master and backport to GCC 11?
Ok for master, and i don't think the backport is necessary.
>
>
On Fri, Aug 6, 2021 at 7:27 PM Richard Biener via Gcc-patches
wrote:
>
> On Fri, Aug 6, 2021 at 11:05 AM Richard Sandiford
> wrote:
> >
> > Richard Biener via Gcc-patches writes:
> > > On Fri, Aug 6, 2021 at 5:32 AM liuhongt wrote:
> > >>
> > >> Hi:
> > >> ---
> > >> OK, I think sth is amiss
On Tue, Aug 3, 2021 at 7:12 PM Hongtao Liu wrote:
>
> On Tue, Aug 3, 2021 at 6:20 PM Richard Biener
> wrote:
> >
> > On Tue, Aug 3, 2021 at 11:20 AM Richard Biener
> > wrote:
> > >
> > > On Wed, Jul 28, 2021 at 4:51 AM Hongtao Liu via Gcc-patches
On Wed, Jul 14, 2021 at 8:38 PM H.J. Lu wrote:
>
> On Tue, Jul 13, 2021 at 9:35 PM Hongtao Liu wrote:
> >
> > On Wed, Jul 14, 2021 at 10:34 AM liuhongt wrote:
> > >
> > > By optimizing vector movement to broadcast in ix86_expand_vector_move
> >
On Tue, Aug 3, 2021 at 10:44 AM Hongtao Liu wrote:
>
> On Tue, Aug 3, 2021 at 3:34 AM Joseph Myers wrote:
> >
> > On Mon, 2 Aug 2021, liuhongt via Gcc-patches wrote:
> >
> > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> > > index 7979e
On Fri, Aug 6, 2021 at 12:59 PM Hongtao Liu wrote:
>
> On Fri, Aug 6, 2021 at 11:44 AM Andrew Pinski via Gcc-patches
> wrote:
> >
> > On Thu, Aug 5, 2021 at 8:33 PM liuhongt via Gcc-patches
> > wrote:
> > >
> > > Hi:
> > > ---
> >
On Thu, Aug 5, 2021 at 5:20 AM Segher Boessenkool
wrote:
>
> On Wed, Aug 04, 2021 at 11:22:53AM +0100, Richard Sandiford wrote:
> > Segher Boessenkool writes:
> > > On Wed, Aug 04, 2021 at 10:10:36AM +0100, Richard Sandiford wrote:
> > >> Richard Biener writes:
> > >> > Alternatively only
On Fri, Aug 6, 2021 at 11:44 AM Andrew Pinski via Gcc-patches
wrote:
>
> On Thu, Aug 5, 2021 at 8:33 PM liuhongt via Gcc-patches
> wrote:
> >
> > Hi:
> > ---
> > OK, I think sth is amiss here upthread. insv/extv do look like they
> > are designed
> > to work on integer modes (but docs do not
On Thu, Aug 5, 2021 at 5:24 PM Richard Biener
wrote:
>
> On Thu, Aug 5, 2021 at 9:25 AM Hongtao Liu wrote:
> >
> > On Wed, Aug 4, 2021 at 7:28 PM Richard Biener
> > wrote:
> > >
> > > On Wed, Aug 4, 2021 at 4:39 AM Hongtao Liu wrote:
> > >
On Thu, Aug 5, 2021 at 3:31 PM Hongtao Liu wrote:
>
> On Wed, Aug 4, 2021 at 7:28 PM Richard Biener
> wrote:
> >
> > On Wed, Aug 4, 2021 at 4:39 AM Hongtao Liu wrote:
> > >
> > > On Mon, Aug 2, 2021 at 2:31 PM liuhongt wrote:
> > > >
> >
On Wed, Aug 4, 2021 at 7:28 PM Richard Biener
wrote:
>
> On Wed, Aug 4, 2021 at 4:39 AM Hongtao Liu wrote:
> >
> > On Mon, Aug 2, 2021 at 2:31 PM liuhongt wrote:
> > >
> > > gcc/ChangeLog:
> > >
> > > * config/i386/i386-modes.def (F
On Wed, Aug 4, 2021 at 8:39 PM liuhongt wrote:
>
> Hi:
> Together with the previous 3 patches, all cond_op expanders of vector
> modes are supported (if they have a corresponding avx512 mask instruction).
Oh, after double check, I realize there're still shift instructions
left, will support in
On Mon, Aug 2, 2021 at 2:31 PM liuhongt wrote:
>
> gcc/ChangeLog:
>
> * config/i386/i386-modes.def (FLOAT_MODE): Define ieee HFmode.
> * config/i386/i386.c (enum x86_64_reg_class): Add
> X86_64_SSEHF_CLASS.
> (merge_classes): Handle X86_64_SSEHF_CLASS.
>
On Mon, Aug 2, 2021 at 2:44 PM liuhongt wrote:
>
> From: "Guo, Xuepeng"
>
> gcc/ChangeLog:
>
> * common/config/i386/cpuinfo.h (get_available_features):
> Detect FEATURE_AVX512FP16.
> * common/config/i386/i386-common.c
> (OPTION_MASK_ISA_AVX512FP16_SET,
>
On Tue, Aug 3, 2021 at 6:20 PM Richard Biener
wrote:
>
> On Tue, Aug 3, 2021 at 11:20 AM Richard Biener
> wrote:
> >
> > On Wed, Jul 28, 2021 at 4:51 AM Hongtao Liu via Gcc-patches
> > wrote:
> > >
> > > On Tue, Jul 27, 2021 at 9:54 AM Hongtao Liu
On Tue, Aug 3, 2021 at 4:03 PM Uros Bizjak via Gcc-patches
wrote:
>
> On Mon, Aug 2, 2021 at 7:47 PM H.J. Lu wrote:
> >
> > In 64-bit mode, use XMM31 for scratch SSE register to avoid vzeroupper
> > if possible.
> >
> > gcc/
> >
> > * config/i386/i386.c (ix86_gen_scratch_sse_rtx): In
On Tue, Aug 3, 2021 at 3:34 AM Joseph Myers wrote:
>
> On Mon, 2 Aug 2021, liuhongt via Gcc-patches wrote:
>
> > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> > index 7979e240426..dc673c89bc8 100644
> > --- a/gcc/config/i386/i386.c
> > +++ b/gcc/config/i386/i386.c
> > @@ -23352,6
On Tue, Aug 3, 2021 at 1:48 AM H.J. Lu via Gcc-patches
wrote:
>
> In 64-bit mode, use XMM31 for scratch SSE register to avoid vzeroupper
> if possible.
>
> gcc/
>
> * config/i386/i386.c (ix86_gen_scratch_sse_rtx): In 64-bit mode,
> try XMM31 to avoid vzeroupper.
LGTM.
>
>
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