On Mon, Aug 2, 2021 at 6:20 PM Richard Biener via Gcc-patches
wrote:
>
> On Mon, Aug 2, 2021 at 6:33 AM liuhongt wrote:
> >
> > Hi:
> > This patch supports cond_add/sub/mul/div expanders for vector
> > float/double.
> > There're still cond_fma/fms/fnms/fma/max/min/xor/ior/and left which I
On Fri, Jul 30, 2021 at 5:30 AM Joseph Myers wrote:
>
> On Thu, 29 Jul 2021, Hongtao Liu via Gcc-patches wrote:
>
> > > Rather than using FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 whenever TARGET_SSE2
> > > (i.e. whenever the type is available), it might make more sense to f
On Fri, Jul 30, 2021 at 4:58 AM Joseph Myers wrote:
>
> On Tue, 27 Jul 2021, Hongtao Liu via Gcc-patches wrote:
>
> > modified gcc/emit-rtl.c
> > @@ -928,6 +928,10 @@ validate_subreg (machine_mode omode, machine_mode
> > imode,
> > fix them all.
On Thu, Jul 29, 2021 at 12:53 PM Hongtao Liu wrote:
>
> On Thu, Jul 29, 2021 at 5:57 AM Joseph Myers wrote:
> >
> > On Wed, 21 Jul 2021, liuhongt via Gcc-patches wrote:
> >
> > > @@ -23254,13 +23337,15 @@ ix86_get_excess_precision (enum
> > > excess_p
On Thu, Jul 29, 2021 at 5:57 AM Joseph Myers wrote:
>
> On Wed, 21 Jul 2021, liuhongt via Gcc-patches wrote:
>
> > @@ -23254,13 +23337,15 @@ ix86_get_excess_precision (enum
> > excess_precision_type type)
> > provide would be identical were it not for the unpredictable
> >
On Wed, Jul 28, 2021 at 8:36 PM Richard Biener
wrote:
>
> On Wed, Jul 28, 2021 at 10:35 AM liuhongt wrote:
> >
> > Hi:
> > As described in PR 39821, WIDEN_MULT_EXPR should use a different cost
> > model from MULT_EXPR, this patch add ix86_widen_mult_cost for that.
> > Reference basis for the
On Wed, Jul 28, 2021 at 10:46 AM H.J. Lu wrote:
>
> On Tue, Jul 27, 2021 at 7:02 PM Hongtao Liu wrote:
> >
> > On Tue, Jul 27, 2021 at 10:46 PM H.J. Lu via Gcc-patches
> > wrote:
> > >
> > > There is no SSE <-> AVX transition penalty if the upp
On Tue, Jul 27, 2021 at 9:54 AM Hongtao Liu wrote:
>
> On Mon, Jul 26, 2021 at 4:49 PM Hongtao Liu wrote:
> >
> > Correct mail list, please reply under this email.
> >
> > On Mon, Jul 26, 2021 at 4:47 PM liuhongt wrote:
> > >
> > > Hi:
> >
On Tue, Jul 27, 2021 at 10:46 PM H.J. Lu via Gcc-patches
wrote:
>
> There is no SSE <-> AVX transition penalty if the upper bits of YMM/ZMM
> registers are unchanged and YMM/ZMM store doesn't change the upper bits
> of YMM/ZMM registers.
>
> 1. Since zeroing YMM/ZMM register is implemented with
On Tue, Jul 27, 2021 at 6:39 PM Jakub Jelinek wrote:
>
> On Tue, Jul 27, 2021 at 06:33:24PM +0800, Hongtao Liu wrote:
> > > AVX2 introduced vector >> vector shifts, but unfortunately for
> > > V{2,4}DImode
> > > it only supports logical and not arithmetic
On Tue, Jul 27, 2021 at 4:11 PM Jakub Jelinek wrote:
>
> Hi!
>
> AVX2 introduced vector >> vector shifts, but unfortunately for V{2,4}DImode
> it only supports logical and not arithmetic shifts, only AVX512F for
> V8DImode or AVX512VL for V{2,4}DImode fixed that omission.
> Earlier in GCC12 cycle
On Thu, Jul 22, 2021 at 8:14 PM Richard Biener
wrote:
>
> On Wed, Jul 21, 2021 at 9:43 AM liuhongt wrote:
> >
> > gcc/ChangeLog:
> >
> > * optabs-query.c (get_best_extraction_insn): Use word_mode for
> > HF field.
> >
> > libgcc/ChangeLog:
> >
> > *
On Mon, Jul 26, 2021 at 4:49 PM Hongtao Liu wrote:
>
> Correct mail list, please reply under this email.
>
> On Mon, Jul 26, 2021 at 4:47 PM liuhongt wrote:
> >
> > Hi:
> > As decribled in PR, the pinsr instruction has poor throughput in SKX
> > and C
Correct mail list, please reply under this email.
On Mon, Jul 26, 2021 at 4:47 PM liuhongt wrote:
>
> Hi:
> As decribled in PR, the pinsr instruction has poor throughput in SKX
> and CLX, which leads to worse performance in vectorization in some cases.
> This patch adds a cost member named
On Wed, Jul 14, 2021 at 8:27 PM H.J. Lu wrote:
>
> On Fri, Jun 25, 2021 at 5:39 AM H.J. Lu wrote:
> >
> > On Fri, Jun 25, 2021 at 12:50 AM Uros Bizjak wrote:
> > >
> > > On Fri, Jun 25, 2021 at 4:51 AM Hongtao Liu wrote:
> > > >
> > &g
On Fri, Jul 23, 2021 at 1:13 PM Hongtao Liu wrote:
>
> On Thu, Jul 1, 2021 at 2:18 PM liuhongt wrote:
> >
> > From: "H.J. Lu"
> >
> > 1. FP16 vector xor/ior/and/andnot/abs/neg
> > 2. FP16 scalar abs/neg/copysign/xorsign
> >
> >
On Thu, Jul 1, 2021 at 2:18 PM liuhongt wrote:
>
> From: "H.J. Lu"
>
> 1. FP16 vector xor/ior/and/andnot/abs/neg
> 2. FP16 scalar abs/neg/copysign/xorsign
>
> gcc/ChangeLog:
>
> * config/i386/i386-expand.c (ix86_expand_fp_absneg_operator):
> Handle HFmode.
>
On Thu, Jul 1, 2021 at 2:18 PM liuhongt wrote:
>
> gcc/ChangeLog:
>
> * config/i386/i386-features.c (i386-features.c): Handle
> E_HFmode.
> * config/i386/i386.md (sqrthf2): New expander.
> (*sqrt2_sse): Extend to MODEFH.
> * config/i386/sse.md
>
On Fri, Jul 23, 2021 at 10:41 AM H.J. Lu via Gcc-patches
wrote:
>
> Don't return hard register in ix86_gen_scratch_sse_rtx when LRA is in
> progress to avoid ICE when there are no available hard registers for
> LRA.
>
LGTM.
> gcc/
>
> PR target/101504
> * config/i386/i386.c
On Thu, Jul 22, 2021 at 8:34 PM H.J. Lu via Gcc-patches
wrote:
>
> For
>
> (set (reg:V32QI 108)
> (const_vector:V32QI [
> (const_int -1 [0x]) repeated x32
> ])) "x.c":15:5 1573 {movv32qi_internal}
> (expr_list:REG_EQUIV (const_vector:V32QI
On Wed, Jul 21, 2021 at 3:44 PM liuhongt wrote:
>
> gcc/ChangeLog:
>
> * config/i386/avx512fp16intrin.h (_mm_set_ph): New intrinsic.
> (_mm256_set_ph): Likewise.
> (_mm512_set_ph): Likewise.
> (_mm_setr_ph): Likewise.
> (_mm256_setr_ph): Likewise.
>
On Wed, Jul 21, 2021 at 6:35 PM Uros Bizjak wrote:
>
> On Wed, Jul 21, 2021 at 9:43 AM liuhongt wrote:
> >
> > gcc/ChangeLog:
> >
> > * config/i386/i386-modes.def (FLOAT_MODE): Define ieee HFmode.
> > * config/i386/i386.c (enum x86_64_reg_class): Add
> >
On Wed, Jul 14, 2021 at 8:38 PM H.J. Lu wrote:
>
> On Tue, Jul 13, 2021 at 9:35 PM Hongtao Liu wrote:
> >
> > On Wed, Jul 14, 2021 at 10:34 AM liuhongt wrote:
> > >
> > > By optimizing vector movement to broadcast in ix86_expand_vector_move
> >
On Wed, Jul 21, 2021 at 4:16 PM Richard Biener wrote:
>
> On Wed, 21 Jul 2021, Hongtao Liu wrote:
>
> > On Tue, Jul 20, 2021 at 3:38 PM Richard Biener wrote:
> > >
> > > On Tue, 20 Jul 2021, Hongtao Liu wrote:
> > >
> > > > On Fri,
On Tue, Jul 20, 2021 at 3:38 PM Richard Biener wrote:
>
> On Tue, 20 Jul 2021, Hongtao Liu wrote:
>
> > On Fri, Jul 16, 2021 at 5:11 PM Richard Biener wrote:
> > >
> > > On Thu, 15 Jul 2021, Richard Biener wrote:
> > >
> > > > On Thu, 1
On Tue, Jul 20, 2021 at 9:41 PM Uros Bizjak wrote:
>
> On Tue, Jul 20, 2021 at 2:33 PM liuhongt wrote:
> >
> > Hi:
> > As mention in
> > https://gcc.gnu.org/pipermail/gcc-patches/2021-July/575420.html
> >
> > cut start-
> > > note for the lowpart we can just view-convert away the
On Tue, Jul 20, 2021 at 3:38 PM Richard Biener wrote:
>
> On Tue, 20 Jul 2021, Hongtao Liu wrote:
>
> > On Fri, Jul 16, 2021 at 5:11 PM Richard Biener wrote:
> > >
> > > On Thu, 15 Jul 2021, Richard Biener wrote:
> > >
> > > > On Thu, 1
On Fri, Jul 16, 2021 at 5:11 PM Richard Biener wrote:
>
> On Thu, 15 Jul 2021, Richard Biener wrote:
>
> > On Thu, 15 Jul 2021, Richard Biener wrote:
> >
> > > OK, guess I was more looking at
> > >
> > > #define N 32
> > > int foo (unsigned long *a, unsigned long * __restrict b,
> > >
On Thu, Jul 15, 2021 at 8:33 PM Richard Biener wrote:
>
> The following defaults --param vect-partial-vector-usage to zero
> for x86_64 matching existing behavior where support for this
> is not present.
>
> OK for trunk?
>
Ok.
> Thanks,
> Richard/
>
> 2021-07-15 Richard Biener
>
> *
On Thu, Jul 15, 2021 at 7:48 PM Richard Biener wrote:
>
> On Thu, 15 Jul 2021, Hongtao Liu wrote:
>
> > On Thu, Jul 15, 2021 at 6:45 PM Richard Biener via Gcc-patches
> > wrote:
> > >
> > > On Thu, Jul 15, 2021 at 12:30 PM Richard Biener wrote:
> > &
On Fri, Jul 16, 2021 at 1:30 AM H.J. Lu via Gcc-patches
wrote:
>
> In a single SET, all bits of the source YMM/ZMM register are zero when
>
> 1. The source is contant zero.
> 2. The source YMM/ZMM operand are defined from contant zero.
>
> and we don't set AVX_U128_DIRTY.
>
> gcc/
>
> PR
On Thu, Jul 15, 2021 at 6:45 PM Richard Biener via Gcc-patches
wrote:
>
> On Thu, Jul 15, 2021 at 12:30 PM Richard Biener wrote:
> >
> > The following extends the existing loop masking support using
> > SVE WHILE_ULT to x86 by proving an alternate way to produce the
> > mask using
On Thu, Jul 15, 2021 at 2:58 PM Wang, Pengfei wrote:
>
> It seems Clang doesn't support -fexcess-precision=xxx:
> https://github.com/llvm/llvm-project/blob/main/clang/test/Driver/clang_f_opts.c#L403
>
> Thanks
> Pengfei
>
> -Original Message-
> From: Hongtao Liu
er
> via llvm-dev
> Sent: Wednesday, July 14, 2021 11:32 PM
> To: Hongtao Liu
> Cc: Jakub Jelinek ; llvm-dev ;
> Liu, Hongtao ; gcc-patches@gcc.gnu.org; Joseph Myers
>
> Subject: Re: [llvm-dev] [PATCH 0/2] Initial support for AVX512FP16
>
>
>
> On Wed, Jul 1
> >
> Set excess_precision_type to FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 to
> round after each operation could keep semantics right.
> And I'll document the behavior difference between soft-fp and
> AVX512FP16 instruction for exceptions.
I got some feedback from my colleague who's working on
On Wed, Jul 14, 2021 at 2:39 PM Matthias Kretz wrote:
>
> On Wednesday, 14 July 2021 07:18:29 CEST Hongtao Liu via Gcc-help wrote:
> > On Wed, Jul 14, 2021 at 1:15 PM Hongtao Liu wrote:
> > > Hi:
> > > The original problem was that some users wanted the cmdline
On Wed, Jul 14, 2021 at 1:15 PM Hongtao Liu wrote:
>
> Hi:
> The original problem was that some users wanted the cmdline option
> -ffast-math not to act on intrinsic production code. .i.e for codes
> like
>
> #include
> __m256d
> foo2 (__m256d a, __m256d b, __m256d
Hi:
The original problem was that some users wanted the cmdline option
-ffast-math not to act on intrinsic production code. .i.e for codes
like
#include
__m256d
foo2 (__m256d a, __m256d b, __m256d c, __m256d d)
{
__m256d tmp = _mm256_add_pd (a, b);
tmp = _mm256_sub_pd (tmp, c);
tmp =
On Wed, Jul 14, 2021 at 10:34 AM liuhongt wrote:
>
> By optimizing vector movement to broadcast in ix86_expand_vector_move
> during pass_expand, pass_reload/LRA can automatically generate an avx512
> embedded broadcast, pass_cpb is not needed.
>
> Considering that in the absence of avx512f,
On Mon, Jul 12, 2021 at 4:14 PM Xionghu Luo via Gcc-patches
wrote:
>
>
>
> On 2021/7/7 21:20, Richard Biener wrote:
> > On Tue, Jun 29, 2021 at 11:19 AM Xionghu Luo wrote:
> >>
> >>
> >>
> >> On 2021/6/28 16:25, Richard Biener wrote:
> >>> On Mon, Jun 28, 2021 at 10:07 AM Xionghu Luo wrote:
>
On Thu, Jul 8, 2021 at 7:56 AM Segher Boessenkool
wrote:
>
> On Wed, Jul 07, 2021 at 11:32:59PM +0800, Hongtao Liu wrote:
> > On Wed, Jul 7, 2021 at 10:54 PM Segher Boessenkool
> > wrote:
> > > So, a "FAKE_CALL" is very much a *real* call, on the RTL le
On Thu, Jul 8, 2021 at 7:44 AM Segher Boessenkool
wrote:
>
> On Wed, Jul 07, 2021 at 11:23:48PM +0800, Hongtao Liu wrote:
> > On Wed, Jul 7, 2021 at 10:54 PM Segher Boessenkool
> > wrote:
>
> [ snip some old stuff ]
>
> > > Yeah. This stuff needs a rethink.
On Wed, Jul 7, 2021 at 4:15 PM Richard Biener
wrote:
>
> On Wed, Jul 7, 2021 at 4:40 AM Hongtao Liu via Gcc-patches
> wrote:
> >
> > On Tue, Jul 6, 2021 at 9:37 AM Hongtao Liu wrote:
> > >
> > > On Tue, Jul 6, 2021 at 7:31 AM Segher Boess
On Wed, Jul 7, 2021 at 10:54 PM Segher Boessenkool
wrote:
>
> Hi!
>
> On Wed, Jul 07, 2021 at 10:15:08AM +0200, Richard Biener wrote:
> > On Wed, Jul 7, 2021 at 4:40 AM Hongtao Liu via Gcc-patches
> > wrote:
> > > On Tue, Jul 6, 2021 at 9:37 AM Hongtao Liu w
On Wed, Jul 7, 2021 at 10:54 PM Segher Boessenkool
wrote:
>
> Hi!
>
> On Wed, Jul 07, 2021 at 10:15:08AM +0200, Richard Biener wrote:
> > On Wed, Jul 7, 2021 at 4:40 AM Hongtao Liu via Gcc-patches
> > wrote:
> > > On Tue, Jul 6, 2021 at 9:37 AM Hongtao Liu w
> > > > and I have no easy way to test things there. Handling AVX512
> > > > should be easy as followup though.
Here's the patch adding avx512f tests for FMADDSUB/FMSUBADD slp patterns.
Pushed to the trunk.
--
BR,
Hongtao
From 2dc666974cca3a62686f4d7135ca36c25d61a802 Mon Sep 17 00:00:00 2001
On Tue, Jul 6, 2021 at 9:37 AM Hongtao Liu wrote:
>
> On Tue, Jul 6, 2021 at 7:31 AM Segher Boessenkool
> wrote:
> >
> > Hi!
> >
> > I ran into this in shrink-wrap.c today.
> >
> > On Thu, Jun 03, 2021 at 02:54:07PM +0800, liuhongt via Gcc-patch
On Wed, Jul 7, 2021 at 2:11 AM Joseph Myers wrote:
>
> On Tue, 6 Jul 2021, Hongtao Liu via Gcc-patches wrote:
>
> > There may be inconsistent behavior between soft-fp and avx512fp16
> > instructions if we emulate _Float16 w/ float .
> > i.e
> > 1) for a +
On Fri, Jul 2, 2021 at 4:46 AM Joseph Myers wrote:
>
> Some general comments, following what I said on libc-alpha:
>
>
> 1. Can you confirm that the ABI being used for 64-bit, for _Float16 and
> _Complex _Float16 argument passing and return, follows the current x86_64
> ABI document?
>
>
> 2. Can
On Thu, Jul 1, 2021 at 9:04 PM Jakub Jelinek via Gcc-patches
wrote:
>
> On Thu, Jul 01, 2021 at 02:58:01PM +0200, Richard Biener wrote:
> > > The main issue is complex _Float16 functions in libgcc. If _Float16
> > > doesn't
> > > require -mavx512fp16, we need to compile complex _Float16
On Tue, Jul 6, 2021 at 3:42 PM Richard Biener wrote:
>
> On Tue, 6 Jul 2021, Hongtao Liu wrote:
>
> > On Mon, Jul 5, 2021 at 10:09 PM Richard Biener wrote:
> > >
> > > This adds named expanders for vec_fmaddsub4 and
> > > vec_fmsubadd4 which map to x86
On Mon, Jul 5, 2021 at 10:09 PM Richard Biener wrote:
>
> This adds named expanders for vec_fmaddsub4 and
> vec_fmsubadd4 which map to x86 vfmaddsubXXXp{ds} and
> vfmsubaddXXXp{ds} instructions. This complements the previous
> addition of ADDSUB support.
>
> x86 lacks SUBADD and the negate
On Tue, Jul 6, 2021 at 8:03 AM Jeff Law via Gcc-patches
wrote:
>
>
>
> On 7/5/2021 5:30 PM, Segher Boessenkool wrote:
> > Hi!
> >
> > I ran into this in shrink-wrap.c today.
> >
> > On Thu, Jun 03, 2021 at 02:54:07PM +0800, liuhongt via Gcc-patches wrote:
> >> Use "used" flag for CALL_INSN to
On Tue, Jul 6, 2021 at 7:31 AM Segher Boessenkool
wrote:
>
> Hi!
>
> I ran into this in shrink-wrap.c today.
>
> On Thu, Jun 03, 2021 at 02:54:07PM +0800, liuhongt via Gcc-patches wrote:
> > Use "used" flag for CALL_INSN to indicate it's a fake call. If it's a
> > fake call, it won't have its own
Hi:
pushed to master.
Remove xfail for pr92658-avx512vl.c
Typo of standard pattern name has been fixed by r12-1970, remove those
xfails.
gcc/testsuite/ChangeLog
* gcc.target/i386/pr92658-avx512vl.c: Refine testcase.
diff --git
On Fri, Jul 2, 2021 at 4:03 PM Uros Bizjak wrote:
>
> On Fri, Jul 2, 2021 at 8:25 AM Hongtao Liu wrote:
>
> > > > AVX512FP16 is disclosed, refer to [1].
> > > > There're 100+ instructions for AVX512FP16, 67 gcc patches, for the
> > > > convenien
On Fri, Jul 2, 2021 at 7:48 PM Bernhard Reutner-Fischer via
Gcc-patches wrote:
>
> On 2 July 2021 09:36:54 CEST, Richard Biener via Gcc-patches
> wrote:
> >On Thu, Jul 1, 2021 at 11:26 PM Joseph Myers
> >wrote:
> >>
> >> On Thu, 1 Jul 2021, liuhongt via Gcc-patches wrote:
> >>
> >> > +/*
On Fri, Jul 2, 2021 at 4:19 PM Richard Biener
wrote:
>
> On Fri, Jul 2, 2021 at 10:07 AM Uros Bizjak via Gcc-patches
> wrote:
> >
> > On Fri, Jul 2, 2021 at 8:25 AM Hongtao Liu wrote:
> >
> > > > > AVX512FP16 is disclosed, refer to [1].
> > &
On Fri, Jul 2, 2021 at 3:32 PM Jakub Jelinek wrote:
>
> Hi!
>
> ix86_expand_vector_init_duplicate doesn't handle TImode -> V2TImode
> or TImode -> V4TImode broadcasts, so I think we should punt on TImode
> inner mode in ix86_broadcast_from_integer_constant, otherwise we ICE
> in
On Fri, Jul 2, 2021 at 3:46 PM Richard Biener via llvm-dev
wrote:
>
> On Fri, Jul 2, 2021 at 1:34 AM Jacob Lifshay via Gcc-patches
> wrote:
> >
> > On Thu, Jul 1, 2021, 15:28 H.J. Lu via llvm-dev
> > wrote:
> >
> > > On Thu, Jul 1, 2021 at 3:10 PM Joseph Myers
> > > wrote:
> > > >
> > > > On
On Thu, Jul 1, 2021 at 7:10 PM Uros Bizjak wrote:
>
> [Sorry for double post, gcc-patches address was wrong in original post]
>
> On Thu, Jul 1, 2021 at 7:48 AM liuhongt wrote:
> >
> > Hi:
> > AVX512FP16 is disclosed, refer to [1].
> > There're 100+ instructions for AVX512FP16, 67 gcc
On Thu, Jul 1, 2021 at 5:51 PM Richard Biener via Gcc-patches
wrote:
>
> On Thu, Jul 1, 2021 at 9:20 AM liuhongt via Gcc-patches
> wrote:
>
> How does this look on GIMPLE and why's it not better handled there?
Do you mean in match.pd, i'll try that.
C++ FE doesn't support _FLoat16, and the
On Tue, Jun 29, 2021 at 6:16 AM H.J. Lu wrote:
>
> 1. Update move expanders to convert the CONST_WIDE_INT and CONST_VECTOR
> operands to vector broadcast from an integer with AVX.
> 2. Add ix86_gen_scratch_sse_rtx to return a scratch SSE register which
> won't increase stack alignment requirement
On Tue, Jun 29, 2021 at 6:16 AM H.J. Lu wrote:
>
> Add vec_duplicate expander for SSE2 if we can move from GPR to SSE
> register directly.
>
> * config/i386/i386-expand.c (ix86_expand_vector_init_duplicate):
> Make it global.
> * config/i386/i386-protos.h
On Thu, Jul 1, 2021 at 3:51 PM Hongyu Wang wrote:
>
> For Keylocker aesenc/aesdec intrinsics, current implementation
> moves idata to odata unconditionally, which causes safety issue when
> the instruction meets runtime error. So we add a branch to clear
> odata when ZF is set after instruction
On Thu, Jul 1, 2021 at 1:48 PM liuhongt wrote:
>
> From: "Guo, Xuepeng"
>
> gcc/ChangeLog:
>
> * common/config/i386/cpuinfo.h (get_available_features):
> Detect FEATURE_AVX512FP16.
> * common/config/i386/i386-common.c
> (OPTION_MASK_ISA_AVX512FP16_SET,
>
On Thu, Jul 1, 2021 at 1:48 PM liuhongt wrote:
>
> 1. Add extendhftf2, extendhfxf2, truncxfhf2, trunctfhf2, fixhfti,
> fixunshfti, floattihf and floatuntihf.
> 2. Always add _divhc3.c and _mulhc3.c. If assembler doesn't support
> AVX512FP16, they are empty.
>
> 2019-01-01 H.J. Lu
>
On Thu, Jul 1, 2021 at 1:48 PM liuhongt wrote:
>
> Hi:
> AVX512FP16 is disclosed, refer to [1].
> There're 100+ instructions for AVX512FP16, 67 gcc patches, for the
> convenience of review, we divide the 67 patches into 2 major parts.
> The first part is 2 patches containing basic support
On Wed, Jun 30, 2021 at 5:42 PM Kewen.Lin wrote:
>
> on 2021/6/30 下午4:53, Hongtao Liu wrote:
> > On Mon, Jun 28, 2021 at 3:27 PM Kewen.Lin wrote:
> >>
> >> on 2021/6/28 下午3:20, Hongtao Liu wrote:
> >>> On Mon, Jun 28, 2021 at 3:12 PM Hongtao Liu wrote:
On Mon, Jun 28, 2021 at 3:27 PM Kewen.Lin wrote:
>
> on 2021/6/28 下午3:20, Hongtao Liu wrote:
> > On Mon, Jun 28, 2021 at 3:12 PM Hongtao Liu wrote:
> >>
> >> On Mon, Jun 28, 2021 at 2:50 PM Kewen.Lin wrote:
> >>>
> >>> Hi!
> >
On Mon, Jun 28, 2021 at 3:12 PM Hongtao Liu wrote:
>
> On Mon, Jun 28, 2021 at 2:50 PM Kewen.Lin wrote:
> >
> > Hi!
> >
> > on 2021/6/9 下午1:18, Kewen.Lin via Gcc-patches wrote:
> > > Hi,
> > >
> > > PR100328 has some details about this i
On Mon, Jun 28, 2021 at 2:50 PM Kewen.Lin wrote:
>
> Hi!
>
> on 2021/6/9 下午1:18, Kewen.Lin via Gcc-patches wrote:
> > Hi,
> >
> > PR100328 has some details about this issue, I am trying to
> > brief it here. In the hottest function LBM_performStreamCollideTRT
> > of SPEC2017 bmk 519.lbm_r, there
On Sun, Jun 27, 2021 at 4:02 AM H.J. Lu wrote:
>
> 1. Update move expanders to convert the CONST_WIDE_INT and CONST_VECTO
> operands to vector broadcast from an integer with AVX2.
> 2. Add ix86_gen_scratch_sse_rtx to return a scratch SSE register which
> won't increase stack alignment requirement
On Mon, May 24, 2021 at 12:59 PM Hongtao Liu wrote:
>
> Hi:
> This patch is about to add define_insn_and_split to convert avx512
> mask mov back to pblendv instructions when mask operand is (lt: reg
> const0_rtx).
>
Hi:
Here's the patch I'm going to check in.
gcc/Chan
Hi:
Ater a second thought, I gave up on refactoring blendv's pattern, we
already have vec_mege with const_int mask, integer mask, and
introducing vector mask doesn't look very good.
Here is the final patch I'm going to check in.
Fold __builtin_ia32_pblendvb128 (a, b, c) as VEC_COND_EXPR (c <
On Fri, Jun 25, 2021 at 2:01 PM Hongtao Liu wrote:
>
> I didn't receive
> https://gcc.gnu.org/pipermail/gcc-patches/2021-June/572436.html in my
> gmail account, does anyone know why?
>
>
> >--- a/gcc/config/i386/i386-protos.h
> >+++ b/gcc/config/i386/i386-protos.h
I didn't receive
https://gcc.gnu.org/pipermail/gcc-patches/2021-June/572436.html in my
gmail account, does anyone know why?
>--- a/gcc/config/i386/i386-protos.h
>+++ b/gcc/config/i386/i386-protos.h
>@@ -260,6 +260,7 @@ extern void ix86_expand_mul_widen_hilo (rtx, rtx, rtx,
>bool, bool);
>
On Fri, Jun 25, 2021 at 12:13 AM Uros Bizjak via Gcc-patches
wrote:
>
> On Thu, Jun 24, 2021 at 2:12 PM H.J. Lu wrote:
> >
> > CPUID functions are used to detect CPU features. If vector ISAs
> > are enabled, compiler is free to use them in these functions. Add
> > __attribute__
On Wed, Jun 23, 2021 at 5:08 PM Richard Biener
wrote:
>
> On Wed, Jun 23, 2021 at 10:01 AM Jakub Jelinek wrote:
> >
> > On Wed, Jun 23, 2021 at 09:53:27AM +0200, Richard Biener via Gcc-patches
> > wrote:
> > > On Wed, Jun 23, 2021 at 9:19 AM Hongtao
On Wed, Jun 23, 2021 at 5:55 PM Uros Bizjak wrote:
>
> On Wed, Jun 23, 2021 at 11:41 AM Uros Bizjak wrote:
> >
> > On Wed, Jun 23, 2021 at 11:32 AM Hongtao Liu wrote:
> >
> > > > > > > > Also when allocano cost of GENERAL_REGS
On Wed, Jun 23, 2021 at 4:50 PM Hongtao Liu wrote:
>
> On Wed, Jun 23, 2021 at 3:59 PM Uros Bizjak wrote:
> >
> > On Mon, Jun 21, 2021 at 10:08 AM Hongtao Liu wrote:
> > >
> > > On Mon, Jun 21, 2021 at 3:28 PM Uros Bizjak via Gcc-patches
> > > wro
On Wed, Jun 23, 2021 at 3:59 PM Uros Bizjak wrote:
>
> On Mon, Jun 21, 2021 at 10:08 AM Hongtao Liu wrote:
> >
> > On Mon, Jun 21, 2021 at 3:28 PM Uros Bizjak via Gcc-patches
> > wrote:
> > >
> > > On Mon, Jun 21, 2021 at 6:56 AM liuhongt wrote:
&
On Wed, Jun 23, 2021 at 3:23 PM Hongtao Liu wrote:
>
> Here's the patch I'm going to check in.
>
> The patch will regress pr91838.C with extra options: -march=cascadelake
>
> using T = unsigned char; // or ushort, or uint
> using V [[gnu::vector_size(8)]] = T;
> V f(V x)
we did in
ix86_expand_vec_shift_qihi_constant).
So I guess maybe gimple should handle such situations to avoid
"nonoptimal codegen".
On Mon, May 24, 2021 at 5:49 PM Hongtao Liu wrote:
>
> Hi:
> This patch is about to add expanders for vashl,
> vlshr,
> vashr and vashr.
>
> Besides there's
On Tue, Jun 22, 2021 at 10:43 AM Hongtao Liu wrote:
>
> On Mon, Jun 21, 2021 at 6:05 PM Richard Biener
> wrote:
> >
> > On Thu, Jun 17, 2021 at 8:29 AM liuhongt wrote:
> > >
> > > The patch remove those pro- and demotions when backend support direct
> &
On Mon, Jun 21, 2021 at 6:05 PM Richard Biener
wrote:
>
> On Thu, Jun 17, 2021 at 8:29 AM liuhongt wrote:
> >
> > The patch remove those pro- and demotions when backend support direct
> > optab.
> >
> > For i386: it enables vectorization for vpopcntb/vpopcntw and optimized
> > for vpopcntq.
> >
This is the patch I'm going to push to the trunk.
On Wed, May 12, 2021 at 3:28 PM Hongtao Liu wrote:
>
> ping
>
> On Fri, Apr 30, 2021 at 12:49 PM Hongtao Liu wrote:
> >
> > Hi:
> > For v{,p}expand* When mask is 0, -1, or has all all one bits in its
>
This is the patch I'm going to push to the trunk.
On Wed, May 12, 2021 at 3:29 PM Hongtao Liu wrote:
>
> ping
>
> On Fri, Apr 30, 2021 at 12:42 PM Hongtao Liu wrote:
> >
> > Hi:
> > This patch is to fix ice which was introduced by my
> > r11-5696-g35c4
On Mon, Jun 21, 2021 at 3:28 PM Uros Bizjak via Gcc-patches
wrote:
>
> On Mon, Jun 21, 2021 at 6:56 AM liuhongt wrote:
> >
> > The avx512 supports bitwise operations with mask registers, but the
> > throughput of those instructions is much lower than that of the
> > corresponding gpr version, so
On Wed, Jun 9, 2021 at 2:02 AM H.J. Lu via Gcc-patches
wrote:
>
> 1. Update move expanders to convert the CONST_WIDE_INT and CONST_VECTO
> operands to vector broadcast from an integer with AVX2.
> 2. Add ix86_gen_scratch_sse_rtx to return a scratch SSE register which
> won't increase stack
On Mon, Jun 7, 2021 at 2:22 PM Hongtao Liu wrote:
>
> On Fri, Jun 4, 2021 at 4:18 PM Marc Glisse wrote:
> >
> > On Fri, 4 Jun 2021, Hongtao Liu via Gcc-patches wrote:
> >
> > > On Tue, Jun 1, 2021 at 6:17 PM Marc Glisse wrote:
> > >>
> > >&
On Fri, Jun 4, 2021 at 4:18 PM Marc Glisse wrote:
>
> On Fri, 4 Jun 2021, Hongtao Liu via Gcc-patches wrote:
>
> > On Tue, Jun 1, 2021 at 6:17 PM Marc Glisse wrote:
> >>
> >> On Tue, 1 Jun 2021, Hongtao Liu via Gcc-patches wrote:
> >>
> &
On Fri, Jun 4, 2021 at 1:01 PM Hongtao Liu wrote:
>
> On Tue, Jun 1, 2021 at 6:17 PM Marc Glisse wrote:
> >
> > On Tue, 1 Jun 2021, Hongtao Liu via Gcc-patches wrote:
> >
> > > Hi:
> > > This patch is about to simplify (view_convert:type ~a) < 0
On Fri, Jun 4, 2021 at 2:27 PM Uros Bizjak via Gcc-patches
wrote:
>
> On Thu, Jun 3, 2021 at 8:54 AM liuhongt wrote:
> >
> > When __builtin_ia32_vzeroupper is called explicitly, the corresponding
> > vzeroupper pattern does not carry any CLOBBERS or SETs before LRA,
> > which leads to incorrect
ping
On Mon, May 24, 2021 at 12:56 PM Hongtao Liu wrote:
>
> Hi:
> This patch is about to Fold __builtin_ia32_pblendvb128 (a, b, c) as
> VEC_COND_EXPR (c < 0, b, a), similar for float version but with
> mask operand VIEW_CONVERT_EXPR to same sized integer vectype.
>
&g
On Tue, Jun 1, 2021 at 6:17 PM Marc Glisse wrote:
>
> On Tue, 1 Jun 2021, Hongtao Liu via Gcc-patches wrote:
>
> > Hi:
> > This patch is about to simplify (view_convert:type ~a) < 0 to
> > (view_convert:type a) >= 0 when type is signed integer. Similar fo
Ping
This is a splitted backend patch as a follow up of
https://gcc.gnu.org/pipermail/gcc-patches/2021-June/571545.html
On Thu, Jun 3, 2021 at 2:55 PM liuhongt via Gcc-patches
wrote:
>
> When __builtin_ia32_vzeroupper is called explicitly, the corresponding
> vzeroupper pattern does not carry
Ping,
This is a splitted middle-end patch as a follow up of
https://gcc.gnu.org/pipermail/gcc-patches/2021-June/571544.html
On Thu, Jun 3, 2021 at 2:54 PM liuhongt via Gcc-patches
wrote:
>
> Use "used" flag for CALL_INSN to indicate it's a fake call. If it's a
> fake call, it won't have its own
Please discard this one, sorry for disturbing.
Obviously I'm new to git send-email.
On Wed, Jun 2, 2021 at 1:40 PM liuhongt via Gcc-patches
wrote:
>
> This is the updated patch.
>
>
--
BR,
Hongtao
On Wed, Jun 2, 2021 at 7:07 AM H.J. Lu via Gcc-patches
wrote:
>
> On Tue, Jun 1, 2021 at 7:21 AM Jeff Law wrote:
> >
> >
> >
> > On 6/1/2021 7:29 AM, H.J. Lu via Gcc-patches wrote:
> > > On Tue, Jun 1, 2021 at 6:25 AM Richard Biener
> > > wrote:
> > >> On Tue, Jun 1, 2021 at 3:05 PM H.J. Lu
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