> From: Marcus Shawcroft [mailto:marcus.shawcr...@gmail.com]
> Sent: 19 May 2014 11:45
> To: Ian Bolton
> Cc: gcc-patches
> Subject: Re: [PATCH, AArch64] Fix macro in vdup_lane_2 test case
>
> On 8 May 2014 18:41, Ian Bolton wrote:
>
> > gcc/testsuite
&g
Ping. This may well be classed as "obvious", but that's not
obvious to me, so I request a review. Many thanks.
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Ian Bolton
> Sent: 08 May 2
Ping. This should be relatively simple to review.
Many thanks.
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Ian Bolton
> Sent: 08 May 2014 18:36
> To: gcc-patches
> Subject: [PATCH, AArch64] Use MOVN
verified impact on a number of examples.
OK for trunk?
Cheers,
Ian
2014-05-12 Ian Bolton
* config/aarch64/aarch64-protos.h
(aarch64_hard_regno_caller_save_mode): New prototype.
* config/aarch64/aarch64.c (aarch64_hard_regno_caller_save_mode):
New function.
* config
This patch fixes a defective macro definition, based on correct
definition in similar testcases. The test currently passes
through luck rather than correctness.
OK for commit?
Cheers,
Ian
2014-05-08 Ian Bolton
gcc/testsuite
* gcc.target/aarch64/vdup_lane_2.c (force_simd): Emit an
does the immediate in two instructions is still used.)
Tested on standard gcc regressions and the attached test case.
OK for commit?
Cheers,
Ian
2014-05-08 Ian Bolton
gcc/
* config/aarch64/aarch64.c (aarch64_expand_mov_immediate):
Use MOVN when top-most half-word (and only
> Hi,
>
> On 28 January 2014 13:10, Ramana Radhakrishnan
> wrote:
> > On Fri, Jan 24, 2014 at 5:16 PM, Ian Bolton
> wrote:
> >> Hi there!
> >>
> >> An existing optimisation for Thumb-2 converts t32 encodings to
> >> t16 encodings to reduc
> -Original Message-
> From: Richard Earnshaw
> Sent: 21 March 2014 13:57
> To: Ian Bolton
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH, ARM] Optimise NotDI AND/OR ZeroExtendSI for ARMv7A
>
> On 19/03/14 16:53, Ian Bolton wrote:
> > This is a
:SI))
--> the top half becomes zero.
I've added test cases for both of these and also the existing
anddi_notdi patterns. The tests all pass.
Full regression runs passed.
OK for stage 1?
Cheers,
Ian
2014-03-19 Ian Bolton
gcc/
* config/arm/arm.md (*anddi_notdi_zesidi):
ndard regressions passed.
OK for trunk or stage 1?
Cheers,
Ian
10-03-2014 Ian Bolton
* gcc/c-family/c-opts.c (c_common_post_options): Don't override
-ffp-contract=fast if unsafe-math-optimizations is on.diff --git a/gcc/c-family/c-opts.c b/gcc/c-family/c-opts.c
index b7478f3..92ba
not using general regs only.
Tested on simple testcase to ensure __ARM_NEON was defined.
OK for trunk?
Cheers,
Ian
2014-02-24 Ian Bolton
* config/aarch64/aarch64.h: Define __ARM_NEON by default if we are
not using general regs only.diff --git a/gcc/config/aarch64/aarch64.h b/
ks for correct number of
ORN instructions in the assembly.
Regressions passed.
OK for stage 1?
2014-02-19 Ian Bolton
gcc/
* config/arm/thumb2.md (*iordi_notdi_di): New pattern.
(*iordi_notzesidi): New pattern.
(*iordi_notsesidi_di): New pattern.
testsuite/
* gcc.
.
> >
> > OK for commit?
> >
> > Cheers,
> > Ian
> >
> >
> > 2014-02-13 Ian Bolton
> >
> > testsuite/
> > * gcc.target/arm/pr59858.c: Skip test if -mfloat-abi=hard.
> >
> >
> > pr59858-skip-if-hard-fl
Hi,
The pr59858.c testcase explicitly sets -msoft-float which is incompatible
with our -mfloat-abi=hard variant.
This patch therefore should not be run if you have -mfloat-abi=hard.
Tested with both variations for arm-none-eabi build.
OK for commit?
Cheers,
Ian
2014-02-13 Ian Bolton
stage 1?
Cheers,
Ian
2014-02-05 Ian Bolton
testsuite/
* gcc.dg/tree-ssa/pr59597.c: Make called function static so that
expected outcome works for PIC variants too.diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr59597.c
b/gcc/testsuite/gcc.dg/tree-ssa/pr59597.c
index 814d299
regressions and performance has improved for
the workloads tested on cortex-a15. (It might be beneficial to
other processors too, but that has not been investigated yet.)
OK for stage 1?
Cheers,
Ian
2014-01-24 Ian Bolton
gcc/
* config/arm/arm-protos.h (tune_params): New struct
VM for practical purposes. (The Thumb
> > encoding in Mark's patch already matched LLVM.)
> >
> >
> > OK for trunk?
> >
> > Cheers,
> > Ian
> >
> >
> > 2013-12-04 Ian Bolton
> >Mark Mitchell
> >
> > gcc/
> On Wed, 4 Dec 2013, Ian Bolton wrote:
>
> > The main update, other than cosmetic differences, is that we've
> chosen
> > the same ARM encoding as LLVM for practical purposes. (The Thumb
> > encoding in Mark's patch already matched LLVM.)
>
> Do t
update, other than cosmetic differences, is that we've chosen
the same ARM encoding as LLVM for practical purposes. (The Thumb
encoding in Mark's patch already matched LLVM.)
OK for trunk?
Cheers,
Ian
2013-12-04 Ian Bolton
Mark Mitchell
gcc/
* config/arm/ar
NO_REGS (which leads to literal pool) is returned, when the immediate
can't be put directly into FP_REGS.
A testcase is included.
Linux regressions all came back good.
OK for trunk?
Cheers,
Ian
2013-09-04 Ian Bolton
gcc/
* config/aarch64/aarch64.c (aarch64_preferred_reload_
for trunk?
Cheers,
Ian
2013-07-30 Ian Bolton
gcc/
* config/aarch64/aarch64.c (aarch64_secondary_reload)): Handle
constant into FP_REGs that is not valid for MOVI.
testsuite/
* gcc.target/aarch64/movdi_1.c: New test.diff --git a/gcc/config/aarch64/aarch64.c b/gcc
Support added for scalar NEG instruction in vector registers.
Execution testcase included.
Tested on usual GCC Linux regressions.
OK for trunk?
Cheers,
Ian
2013-07-23 Ian Bolton
gcc/
* config/aarch64/aarch64-simd.md (neg2): Offer alternative
that uses vector registers
> On 12 Jul 2013, at 19:49, Ian Bolton wrote:
>
> >
> > 2013-07-12 Ian Bolton
> >
> > gcc/
> > * config/aarch64/arm_neon.h (vabs_s64): New function.
> >
> > testsuite/
> > * gcc.target/aarch64/scalar_intrinsics.c (test_vabs_s64)
This patch implements the following intrinsic:
int64x1_t vabs_s64 (int64x1 a)
It uses __builtin_llabs(), which will lead to "abs Dn, Dm" being generated
for
this now that my other patch has been committed.
Test case added to scalar_intrinsics.c.
OK for trunk?
Cheers,
Ian
2013-
Hi,
We don't currently generate BFXIL on AArch64. This patch addresses that,
by adding a pattern in the backend.
It comes with test cases for little and big endian.
Tested on little-endian linux and bare-metal, and big-endian linux.
OK for trunk?
Cheers,
Ian
2013-06-27 Ian Bolton
Hi,
I'm adding support for abs standard pattern name for DI mode,
via the ABS instruction in FP registers and the EOR/SUB combo
in GP registers.
Regression tests for Linux and bare-metal all passed.
OK for trunk?
Cheers,
Ian
2013-06-25 Ian Bolton
gcc/
* config/aarch64/aa
supported.
I've tested these two tests on little and big. All was OK.
OK for trunk?
Cheers,
Ian
2013-06-24 Ian Bolton
* gcc.target/config/aarch64/insv_1.c: Update to show it doesn't work
on big endian.
* gcc.target/config/aarch64/insv_2.c: New test for
g for aarch64_print_operand, as is done for
vector immediates.
Regression runs have passed for Linux and bare-metal.
OK for trunk?
Cheers,
Ian
2013-06-03 Ian Bolton
gcc/
* config/aarch64/aarch64.md (*mov_aarch64): Call
into function to generate MOVI instruction.
* config/aa
(This patch is the fourth of five, where the first 4 do some clean-up and
the last fixes a bug with scalar MOVI. The bug fix without the clean-up
was particularly ugly!)
I think the changelog says it all here. Nothing major, just tidying up.
OK for trunk?
Cheers,
Ian
2013-06-03 Ian
RTX operands.
Specifically, I've changed the set of pointers that are passed in
(it's now a struct) and the caller prints out the immediate value
directly instead of letting operand[1] get fudged.
OK for trunk?
Cheers,
Ian
2013-06-03 Ian Bolton
* config/aarch64
?
Cheers,
Ian
13-06-03 Ian Bolton
* config/aarch64/aarch64.c (aarch64_simd_valid_immediate): No
longer static.
(aarch64_simd_immediate_valid_for_move): Remove.
(aarch64_simd_scalar_immediate_valid_for_move): Update call.
(aarch64_simd_make_constant): Update
?
Cheers,
Ian
13-06-03 Ian Bolton
* config/aarch64/aarch64.c (aarch64_simd_valid_immediate): Change
return type to bool for prototype.
(aarch64_legitimate_constant_p): Check for true instead of not -1.
(aarch64_simd_valid_immediate): Fix up each return to
> On 05/20/2013 11:55 AM, Ian Bolton wrote:
> > I improved this patch during the work I did on the recent insv_imm
> patch
> > (http://gcc.gnu.org/ml/gcc-patches/2013-05/msg01007.html).
>
> Thanks, you cleaned up almost everything on which I would have
> commente
trunk?
Cheers,
Ian
2013-05-22 Ian Bolton
testsuite/
* gcc.target/aarch64/scalar_intrinsics.c (force_simd):
Use a valid instruction.
(test_vdupd_lane_s64): Pass a valid lane argument.
(test_vdupd_lane_u64): Likewise.diff --git a/gcc/testsuite/gcc.target/aarc
>
> Cheers,
> Ian
>
>
> 2013-05-08 Ian Bolton
>
> gcc/
> * config/aarch64/aarch64.md (insv): New define_expand.
> (*insv_reg): New define_insn.
>
> testsuite/
> * gcc.target/aarch64/bfm_1.c: New test.
(This patch did not yet get co
Ian
2013-05-17 Ian Bolton
* config/aarch64/aarch64.c (aarch64_print_operand): Change the X
format
specifier to only display bottom 16 bits.
* config/aarch64/aarch64.md (insv_imm): Allow any-sized
immediate
to match for operand 2, since it will be masked.diff -
Hi,
This patch implements the BFI variant of BFM. In doing so, it also
implements the insv standard pattern.
I've regression tested on bare-metal and linux.
It comes complete with its own compilation and execution testcase.
OK for trunk?
Cheers,
Ian
2013-05-08 Ian Bolton
I previously fixed a bug with the patterns that generate TST.
I added these testcases to make our regression testing more solid.
They've been running on our internal branch for about a month.
OK to commit to trunk?
Cheers,
Ian
2013-05-02 Ian Bolton
* gcc.target/aarch64/ts
> Can we have the patch attached ?
OK
Index: gcc/testsuite/gcc.target/aarch64/bics_1.c
===
--- gcc/testsuite/gcc.target/aarch64/bics_1.c (revision 0)
+++ gcc/testsuite/gcc.target/aarch64/bics_1.c (revision 0)
@@ -0,0 +1,107 @@
+/*
good.
OK for trunk?
Cheers,
Ian
2013-05-01 Ian Bolton
* config/aarch64/aarch64.md (movsi_aarch64): Only allow to/from
S reg when fp attribute set.
(movdi_aarch64): Only allow to/from D reg when fp attribute set.Index: gcc/config/aarch64/aarch
atest patch (attached).
OK to commit?
Cheers,
Ian
2013-05-01 Ian Bolton
gcc/
* config/aarch64/aarch64.md (*and_one_cmpl3_compare0):
New pattern.
(*and_one_cmplsi3_compare0_uxtw): Likewise.
(*and_one_cmpl_3_compare0): Likewise.
(*and_one_cmpl_si3_com
overlap with the lsl based rule.
I've also renamed the testcases in line with the suggested GCC testcase
naming convention.
OK for commit?
Cheers,
Ian
2013-05-01 Ian Bolton
* gcc.target/aarch64/ands_1.c: New test.
* gcc.tar
This patch allows us to load to and store from the S and D registers,
which helps with doing scalar operations in those registers.
This has been regression tested on bare-metal and linux.
OK for trunk?
Cheers,
Ian
2013-04-26 Ian Bolton
* config/aarch64/aarch64.md (movsi_aarch64
With these patterns, we can now generate BICS in the appropriate places.
I've included test cases.
This has been run on linux and bare-metal regression tests.
OK to commit?
Cheers,
Ian
2013-04-26 Ian Bolton
gcc/
* config/aarch64/aarch64.md (*and_one_cmpl3_compare0):
heers,
Ian
2013-04-26 Ian Bolton
* gcc.target/aarch64/ands.c: New test.
* gcc.target/aarch64/ands2.c: LikewiseIndex: gcc/testsuite/gcc.target/aarch64/ands2.c
===
--- gcc/testsuite/gcc.target/aarch64/ands2.c(revis
Since this is a bug fix, I'll need to backport to 4.8.
Is that OK?
Cheers,
Ian
> OK
> /Marcus
>
> On 20 March 2013 17:21, Ian Bolton wrote:
> > MOVK should not be generated with a negative immediate, which
> > the assembler rightfully rejects.
> >
>
This patch enables Redundant Extension Elimination pass for AArch64.
Testing shows no regressions on linux and bare-metal.
In terms of performance impact, it reduces code-size for some benchmarks
and makes no difference on others.
OK to commit to trunk?
Cheers,
Ian
2013-04-24 Ian Bolton
generated there unless LR
gets clobbered in the leaf for some reason. (I have testcases here to
check for that.)
OK to commit to trunk?
Cheers,
Ian
2013-03-28 Ian Bolton
gcc/
* config/aarch64/aarch64.md (aarch64_can_eliminate): Only keep
frame record when required.
testsuite
MOVK should not be generated with a negative immediate, which
the assembler rightfully rejects.
This patch makes MOVK output its 2nd operand in hex instead.
Tested on bare-metal and linux.
OK for trunk?
Cheers,
Ian
2013-03-20 Ian Bolton
gcc/
* config/aarch64/aarch64.c
> Please consider this as a reminder to review the patch posted at
> following link:-
> http://gcc.gnu.org/ml/gcc-patches/2013-01/msg01374.html
>
> The patch is slightly modified to use CC_NZ mode instead of CC.
>
> Please review the patch and let me know if its okay?
>
Hi Naveen,
With the CC_
We couldn't generate SBC for AArch64 ... until now!
This really patch includes the main pattern, a zero_extend form
of it and a test.
Full regression testing for Linux and bare-metal passed.
OK for trunk stage-1?
Thanks,
Ian
2013-03-14 Ian Bolton
gcc/
* config/aarch64/aarch
13-03-14 Ian Bolton
gcc/
* config/aarch64/aarch64.md (*ror3_insn): New pattern.
(*rorsi3_insn_uxtw): Likewise.
testsuite/
* gcc.target/aarch64/ror.c: New test.
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index ef1c0f3..367c0e3 100644
---
We couldn't generate EXTR for AArch64 ... until now!
This patch includes the pattern and a test.
Full regression testing for Linux and bare-metal passed.
OK for trunk stage-1?
Thanks,
Ian
2013-03-14 Ian Bolton
gcc/
* config/aarch64/aarch64.md (*extr5_insn): New pa
The mode for AND should really be CC_NZ, so I fixed that up and in the TST
patterns that (erroneously) expected it to be CC mode.
It has been tested on linux and bare-metal.
OK to commit to trunk (as bug fix)?
Thanks.
Ian
13-02-01 Ian Bolton
* config/aarch64/aarch64.c
continues the
work of one already committed. :)
This has been regression-tested for linux and bare-metal.
OK for trunk and backport to ARM/aarch64-4.7-branch?
Cheers,
Ian
2013-01-15 Ian Bolton
* gcc/config/aarch64/aarch64.md
(*cstoresi_neg_uxtw): New pattern.
(*cmovsi
> Hi Richard,
>
> > + "add\\t%w0, %w2, %w, xt"
> >
> > ^^^ %w1
>
> Got spot. I guess that pattern hasn't fired yet then! I'll fix it.
Now fixed in v3.
> I should have said that I am indeed running with REE enabled. It has
> some impact (about 70 further UXTW removed from
Hi Richard,
> + "add\\t%w0, %w2, %w, xt"
>
> ^^^ %w1
Got spot. I guess that pattern hasn't fired yet then! I'll fix it.
> > This patch significantly reduces the number of redundant
> > uxtw instructions seen in a variety of programs.
> >
> > (There are further patterns th
educes the number of redundant
uxtw instructions seen in a variety of programs.
(There are further patterns that can be done, but I have them
in a separate patch that's still in development.)
OK for trunk and backport to ARM/aarch64-4.7-branch?
Cheers,
Ian
2012-12-13 Ian Bolton
* gcc
It turned out that this patch depended on another one from
earlier, so I have backported that to ARM/aarch64-4.7-branch too.
http://gcc.gnu.org/ml/gcc-patches/2012-04/msg00452.html
Cheers,
Ian
> -Original Message-
> From: Ian Bolton [mailto:ian.bol...@arm.com]
> Sent: 23 Nove
I had already committed my testcase for this for aarch64, but
it depends on this patch that doesn't yet exist in 4.7, so I
backported to our ARM/aarch64-4.7-branch.
Cheers,
Ian
From:
http://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=f811051bf87b1de7804c19c8192
d0d099d157145
diff --git a/gcc/Cha
This patch implements the standard pattern bswaphi2 for AArch64.
Regression tests all pass.
OK for trunk and backport to arm/aarch64-4.7-branch?
Cheers,
Ian
2012-11-16 Ian Bolton
* gcc/config/aarch64/aarch64.md (bswaphi2): New pattern.
* gcc/testsuite/gcc.target/aarch64
A commit I did earlier in the week got truncated somehow, leading
to a broken testcase for AArch64 target.
I've just commited this fix as obvious on trunk and the
arm/aarch64-4.7-branch.
Cheers
Ian
Index: gcc/testsuite/gcc.target/aarch64/csinc-2.c
===
Some changes had been added to gcc/ChangeLog and gcc/testsuite/Changelog
when they should have been recorded in the gcc/Changelog.aarch64 and
gcc/testsuite/Changelog.aarch64 files instead.
Committed as obvious.
Cheers,
Ian
regression tested on trunk.
OK for commit?
Cheers,
Ian
2012-11-06 Ian Bolton
* gcc/config/aarch64/aarch64.md (cmov_insn): Emit
CSINC when one of the alternatives is constant 1.
* gcc/config/aarch64/constraints.md: New constraint.
* gcc/config/aarch64
work.
OK for trunk?
Cheers,
Ian
2012-11-06 Ian Bolton
* gcc/config/aarch64/aarch64.md (*compare_neg): New pattern.
* gcc/testsuite/gcc.target/aarch64/cmn.c: New test.
* gcc/testsuite/gcc.target/aarch64/adds.c: New test.
* gcc/testsuite/gcc.target/aarch64/subs.c: New
cks that the range is valid before allowing
> the pattern to be used.
>
> This has now had full regression testing and all is OK.
>
> OK for aarch64-trunk and aarch64-4_7-branch?
>
> Cheers,
> Ian
>
>
> 2012-10-15 Ian Bolton
>
> * gcc/confi
testing and all is OK.
OK for aarch64-trunk and aarch64-4_7-branch?
Cheers,
Ian
2012-10-15 Ian Bolton
* gcc/config/aarch64/aarch64.md
(_shft_): Restrict based on op2.
-
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index
pand_mov_immediate
function.
My testing showed no regressions for bare-metal or linux.
OK for aarch64-branch and aarch64-4.7-branch?
Cheers,
Ian
2012-09-25 Richard Henderson
Ian Bolton
* config/aarch64/aarch64.c (aarch64_expand_mov_immediate): Fix a
functiona
> Ok. Having dug a bit deeper I think the main problem is that you're
> working against yourself by not handling this pattern right from the
> beginning. You have split the address incorrectly to begin and are
> now trying to recover after the fact.
>
> The following patch seems to do the trick
New version attached with better formatted test cases.
OK for aarch64-branch and aarch64-4.7-branch?
Cheers,
Ian
-
2012-09-18 Ian Bolton
gcc/
* config/aarch64/aarch64.h: Define CTZ_DEFINED_VALUE_AT_ZERO.
* config
> > > diff --git a/gcc/config/aarch64/aarch64.md
> > b/gcc/config/aarch64/aarch64.md
> > > index 33815ff..5278957 100644
> > > --- a/gcc/config/aarch64/aarch64.md
> > > +++ b/gcc/config/aarch64/aarch64.md
> > > @@ -153,6 +153,8 @@
> > > (UNSPEC_CMTST 83) ; Used in aarch64-simd.md.
> >
> > diff --git a/gcc/config/aarch64/aarch64.md
> b/gcc/config/aarch64/aarch64.md
> > index 33815ff..5278957 100644
> > --- a/gcc/config/aarch64/aarch64.md
> > +++ b/gcc/config/aarch64/aarch64.md
> > @@ -153,6 +153,8 @@
> > (UNSPEC_CMTST 83) ; Used in aarch64-simd.md.
> > (UNSPEC_FMAX
heers,
Ian
2012-09-18 Ian Bolton
gcc/
* config/aarch64/aarch64.h: Define CTZ_DEFINED_VALUE_AT_ZERO.
* config/aarch64/aarch64.md (clrsb2): New pattern.
* config/aarch64/aarch64.md (rbit2): New pattern.
* config/aarch64/aarch64.md (ctz2): New pattern.
gcc/test
OK for aarch64-4.7-branch as well?
> -Original Message-
> From: Richard Earnshaw
> Sent: 14 September 2012 18:31
> To: Ian Bolton
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH, AArch64] Implement ffs standard pattern
>
> On 14/09/12 16:26, Ian Bolton wrote:
OK for 4.7 as well?
> -Original Message-
> From: Richard Earnshaw
> Sent: 14 September 2012 18:18
> To: Ian Bolton
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH, AArch64] Implement fnma, fms and fnms standard
> patterns
>
> On 14/09/12 18:05, Ian Bolt
t?
Cheers,
Ian
2012-09-14 Ian Bolton
gcc/
* config/aarch64/aarch64.md (fmsub4): Renamed
to fnma4.
* config/aarch64/aarch64.md (fnmsub4): Renamed
to fms4.
* config/aarch64/aarch64.md (fnmadd4): Renamed
to fnms4.
* config/aarch64/aarch
I've implemented the standard pattern ffs, which leads to
__builtin_ffs being generated with 4 instructions instead
of 5 instructions.
Regression tests and my new test pass.
OK to commit?
Cheers,
Ian
2012-09-14 Ian Bolton
gcc/
* config/aarch64/aarch64.md (csinc3): Make it
> Can you send me the test case you were looking at for this?
See attached. (Most of it is superfluous, but the point is that
we are not using the address to do a memory access.)
Cheers,
Ian
constant-test1.c
Description: Binary data
> From: Richard Henderson [mailto:r...@redhat.com]
> On 09/06/2012 08:06 AM, Ian Bolton wrote:
> > If I don't use my split pattern, I could alter combine to remove the
> > requirement that parent is a MEM.
> >
> > What do you think?
>
> I merely que
> On 2012-08-31 07:49, Ian Bolton wrote:
> > +(define_split
> > + [(set (match_operand:DI 0 "register_operand" "=r")
> > + (const:DI (plus:DI (match_operand:DI 1 "aarch64_valid_symref"
> "S")
> > +
x0
ret
Testing shows no regressions. OK to commit?
2012-08-31 Ian Bolton
* gcc/config/aarch64/aarch64.md: New pattern.diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index a00d3f0..de9c927 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/
have seen up to 1K reduction in code size.
OK to commit?
Cheers,
Ian
2012-07-06 Ian Bolton
* gcc/config/aarch64/aarch64.c (aarch64_print_operand): Use
aarch64_classify_symbolic_expression for classifying operands.
* gcc/config/aarch64/aarch64.c
This patch makes the vfp-1.c testcase work for Thumb. It became broken when
we
restricted the negative offsets allowed for Thumb to fix up a Spec2K failure
some months back. (It was previously possible to generate illegal offsets.)
OK for trunk?
Cheers,
Ian
2011-07-28 Ian Bolton
> Hi,
> I always considered the cgrpah_node_set/varpool_node_set to be
> overengineered
> but they also turned out to be quite ineffective since we do quite a
> lot of
> queries into them during stremaing out.
>
> This patch moves them to pointer_map, like I did for streamer cache.
> While
> doing
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