Re: RISC-V: Fix round_32.c test on RV32

lt wrote: > On Wed, 22 May 2024 12:02:26 PDT (-0700), jeffreya...@gmail.com wrote: > > > > > > On 5/22/24 12:15 PM, Palmer Dabbelt wrote: > >> On Wed, 22 May 2024 11:01:16 PDT (-0700), jeffreya...@gmail.com wrote: > >>> > >>> > >>>

RISC-V: Fix round_32.c test on RV32

d_32.c: Fixed test -- With the best regards Jivan Hakobyan diff --git a/gcc/testsuite/gcc.target/riscv/round_32.c b/gcc/testsuite/gcc.target/riscv/round_32.c index 88ff77aff2e..b74be4e1103 100644 --- a/gcc/testsuite/gcc.target/riscv/round_32.c +++ b/gcc/testsuite/gcc.target/riscv/round_32.c @@

RISC-V: Use convert instructions instead of calling library functions

: * gcc.target/riscv/fix.c: New test. * gcc.target/riscv/round.c: Likewise. * gcc.target/riscv/round_32.c: Likewise. * gcc.target/riscv/round_64.c: Likewise. -- With the best regards Jivan Hakobyan diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index

Re: [V2] New pass for sign/zero extension elimination -- not ready for "final" review

The reason is removing MINUS from safe_for_live_propagation. We did not do it on purpose, will roll back on V3. > On 29 Nov 2023, at 19:46, Xi Ruoyao wrote: > > On Wed, 2023-11-29 at 20:37 +0800, Xi Ruoyao wrote: >>> On Wed, 2023-11-29 at 17:33 +0800, Xi Ruoyao wrote: >>> On Mon,

Re: [RFA] New pass for sign/zero extension elimination

We already noticed it and will roll back in V3 With the best regards Jivan Hakobyan > On 29 Nov 2023, at 21:37, Joern Rennecke wrote: > > Why did you leave out MINUS from safe_for_live_propagation ?

Re: [V2] New pass for sign/zero extension elimination -- not ready for "final" review

"1.0" > > | #define PACKAGE_STRING "GNU C Runtime Library 1.0" > > | #define PACKAGE_BUGREPORT "" > > | #define PACKAGE_URL "http://www.gnu.org/software/libgcc/; > > | /* end confdefs.h. */ > > | > > | int > > | main () > > | { > > | > > | ; > > | return 0; > > | } > > I think the test is maybe backwards? > >/* ?!? How much of this should mirror SET handling, potentially > being shared? */ >if (SUBREG_BYTE (dst).is_constant () && SUBREG_P (dst)) > > Andrew > -- With the best regards Jivan Hakobyan

[COMMITTED] MAINTAINERS: Add myself to write after approval

< car...@google.com> Vineet Gupta Naveen H.S Mostafa Hagog +Jivan Hakobyan Andrew Haley Frederik H

RISC-V: Add type attribute in *_not_const pattern

(*_not_const): Added type attribute -- With the best regards Jivan Hakobyan diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 977be350ce3..f890280c295 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -225,7 +225,9 @@ (define_insn_and_split

[V2] RISC-V: Replace not + bitwise_imm with li + bitwise_not

pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbb-andn-orn-01.c: New test. * gcc.target/riscv/zbb-andn-orn-02.c: Likewise. -- With the best regards Jivan Hakobyan diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 0d126a8ece54aefb

RISC-V: Replace not + bitwise_imm with li + bitwise_not

pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbb-andn-orn-01.c: New test. * gcc.target/riscv/zbb-andn-orn-02.c: Likewise. -- With the best regards Jivan Hakobyan diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 7b55528ee49..209b0afb118 10064

Re: RISC-V: Fix stack_save_restore_1/2 test cases

wrote: > Hi Jivan, > > On 8/24/23 08:45, Jivan Hakobyan via Gcc-patches wrote: > > This patch fixes failing stack_save_restore_1/2 test cases. > > After 6619b3d4c15c commit size of the frame was changed. > > > > > > gcc/testsuite/ChangeLog: > >

RISC-V: Fix stack_save_restore_1/2 test cases

regards Jivan Hakobyan diff --git a/gcc/testsuite/gcc.target/riscv/stack_save_restore_1.c b/gcc/testsuite/gcc.target/riscv/stack_save_restore_1.c index 255ce5f40c9e300cbcc245d69a045bed2b65d02b..0bf64bac767203685ec88c72394ada617d6940d5 100644 --- a/gcc/testsuite/gcc.target/riscv/stack_save_restore_1.c

Re: IRA update_equiv_regs for (was Re: ICE for interim fix for PR/110748)

gt; > > So you might want to look at register pressure sensitive scheduling > first. If you go into x264_r from specint and look at > x264_pixel_satd_8x4. First verify the loops are fully unrolled. If > they are, then look for 32bit loads/stores into the stack. If you have > them, then you're spilling and getting crappy performance. Using > register pressure sensitive scheduling should help significantly. > > We've certainly seen that internally. The plan was to submit a patch to > make register pressure sensitive scheduling the default when the > scheduler is enabled. We just haven't pushed on it. If you can verify > that you're seeing spilling as well, then it'd certainly bolster the > argument that register-pressure-sensitive-scheduling is desirable. > > Jeff > > > > > > > > -- With the best regards Jivan Hakobyan

Re: RISC-V: Folding memory for FP + constant case

Thank you for your effort. I had evaluated only in intrate tests. I am glad to see the same result on Leela. On Tue, Aug 1, 2023 at 11:14 PM Vineet Gupta wrote: > > > On 7/25/23 20:31, Jeff Law via Gcc-patches wrote: > > > > > > On 7/25/23 05:24, Jivan Hakobyan wro

RISC-V: Replace unspec with bitreverse in riscv_brev8_ insn

This small patch replaces unspec opcode with bitreverse in riscv_brev8_ insn. gcc/ChangeLog: * config/riscv/crypto.md (UNSPEC_BREV8): Remov. (riscv_brev8_): Use bitreverse opcode. -- With the best regards Jivan Hakobyan diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv

Re: RISC-V: Folding memory for FP + constant case

y folding cases (5 redundant moves). Besides that, I have checked the build failure on x264_r. It is already fixed on the third version. On Sat, Jul 15, 2023 at 10:16 AM Jeff Law wrote: > > > On 7/12/23 14:59, Jivan Hakobyan via Gcc-patches wrote: > > Accessing local arrays element t

RISC-V: Folding memory for FP + constant case

uctions, .39% of the dynamic count) and dwarfs the regression for gcc (14m instructions, .0012% of the dynamic count). gcc/ChangeLog: * config/riscv/riscv.cc (riscv_legitimize_address): Handle folding. (mem_shadd_or_shadd_rtx_p): New predicate. -- With the best regards Jivan Hakobya

Re: LTO: buffer overflow in lto_output_init_mode_table

; Regards > Robin > -- With the best regards Jivan Hakobyan

LTO: buffer overflow in lto_output_init_mode_table

r size * tree-streamer.cc (streamer_mode_table): Likewise. -- With the best regards Jivan Hakobyan diff --git a/gcc/tree-streamer.cc b/gcc/tree-streamer.cc index ed65a7692e3..a28ef9c7920 100644 --- a/gcc/tree-streamer.cc +++ b/gcc/tree-streamer.cc @@ -35,7 +35,7 @@ along with GCC; see th

[wwwdocs] Broken URL to README in st/cli-be project

In CLI project link to README is broken. This patch fixes that. Discussed in PR110250 -- With the best regards Jivan Hakobyan diff --git a/htdocs/projects/cli.html b/htdocs/projects/cli.html index 380fb031..394832b6 100644 --- a/htdocs/projects/cli.html +++ b/htdocs/projects/cli.html @@ -145,7

[wwwdocs] Broken URL to README.Portability

This patch fixes the link to README.Portability in "GCC Coding Conventions" page -- With the best regards Jivan Hakobyan diff --git a/htdocs/codingconventions.html b/htdocs/codingconventions.html index 9b6d243d..f5a356a8 100644 --- a/htdocs/codingconventions.html ++

Remove MFWRAP_SPEC remnant

This patch removes a remnant of mudflap. gcc/ChangeLog: * config/moxie/uclinux.h (MFWRAP_SPEC): Remove -- With the best regards Jivan Hakobyan diff --git a/gcc/config/moxie/uclinux.h b/gcc/config/moxie/uclinux.h index f7bb62e56c7..a7d371047c4 100644 --- a/gcc/config/moxie/uclinux.h

[RFC] RISC-V: Eliminate extension after for *w instructions

gcc.target/riscv/zbb-rol-ror-03.c: New test -- With the best regards Jivan Hakobyan diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 96d31d92670b27d495dc5a9fbfc07e8767f40976..0430af7c95b1590308648dc4d5aaea78ada71760 100644 --- a/gcc/config/riscv/bitmanip.md ++

RISC-V: Use extension instructions instead of bitwise "and"

stsuite/ChangeLog: * gcc.target/riscv/and-extend-1.c: New test * gcc.target/riscv/and-extend-2.c: New test -- With the best regards Jivan Hakobyan diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index ffcbb9a7589..70f570153ae 100644 --- a/gcc/config/riscv/pr

[v2] RISC-V: Remove masking third operand of rotate instructions

bb-rol-ror-04.c: New test * testsuite/gcc.target/riscv/zbb-rol-ror-05.c: New test * testsuite/gcc.target/riscv/zbb-rol-ror-06.c: New test * testsuite/gcc.target/riscv/zbb-rol-ror-07.c: New test -- With the best regards Jivan Hakobyan diff --git a/gcc/config/riscv/bitmanip.m

RISC-V: Remove masking third operand of rotate instructions

et/riscv/zbb-rol-ror-07.c: New test -- With the best regards Jivan Hakobyan diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index a27fc3e34a1..0fd0cbdeb04 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -351,6 +351,42 @@ "rolw\t%0,%

RISC-V: Eliminate redundant zero extension of minu/maxu operands

gcc/ChangeLog: * config/riscv/bitmanip.md: Added expanders for minu/maxu instructions gcc/testsuite/ChangeLog: * gcc.target/riscv/zbb-min-max-02.c: Updated scanning check. * gcc.target/riscv/zbb-min-max-03.c: New tests. -- With the best regards Jivan Hakobyan diff --git a/gcc/config/ri

RISC-V: avoid splitting small constants in bcrli_nottwobits patterns

: andi a0,a0,-2 andi a0,a0,-257 ret but should be this one: foo: andi a0,a0,-258 ret This patch solves the mentioned issue. -- With the best regards Jivan Hakobyan RISC-V: avoid splitting small constant in *bclri_nottwobits and *bclridisi_nottwobit