RE: [PATCH][X86_64] Separate znver4 insn reservations from older znvers

[Public] Hello, > OK, > thanks! > Honza Thanks! We have pushed the patch. Regards, Tejas

RE: [PATCH][X86_64] Separate znver4 insn reservations from older znvers

[Public] Hello, I have addressed all your comments in this revision of the patch, please find attached and inlined. * I have updated all the latencies with Agner's measurements. * Incorrect pipelines, loads/stores are addressed. * The double pumped avx512 insns take one cycle for 256 half and

RE: [PATCH][X86_64] Separate znver4 insn reservations from older znvers

[Public] Hi, > I think instead of (znver4-fpu)*2 there should be > > znver4-fpu0*2|znver4-fpu1*2|znver4-fpu2*2|znver4-fpu3*2 > > assuming the instruction occupies the same pipe on both cycles (your variant > models as if it can move from one pipe to another). > Also I think it's better to

RE: [PATCH][X86_64] Separate znver4 insn reservations from older znvers

[Public] Hi, Thank you for reviewing the patch. > Hi. I'm still waiting for feedback on fixes for existing models: > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Finbox. > sourceware.org%2Fgcc-patches%2F5ae6fc21-edc6-133-aee2- >

[PATCH][X86_64] Separate znver4 insn reservations from older znvers

[Public] Hi, PFA the patch which adds znver4 instruction reservations separately from older znver versions: * This also models separate div, fdiv and ssediv units accordingly. * Does not blow-up the insn-automata.cc size (it grew from 201502 to 206141 for me.) * The patch successfully builds,

RE: [PATCH] [X86_64]: Enable support for next generation AMD Zen4 CPU

[Public] Hi, > It is not latency. It is reciprocal throughput. For example, the > multiplication instruction has > latency 3 and reciprocal throughput 1, and the corresponding execution unit > can accept a new > multiplication instruction each cycle. In the .md file we are modeling that > by

RE: [PATCH] [X86_64]: Enable support for next generation AMD Zen4 CPU

[Public] Hi, On Mon, Oct 24, 2022 at 4:26 PM Alexander Monakov wrote: > > > This grew insn-automata.cc from 201502 lines to 639968 lines and the > > > build of the automata (genautomata) to several minutes in my dev tree. > > > > Yeah, in my unoptimized

RE: [PATCH] [X86_64]: Enable support for next generation AMD Zen4 CPU

[Public] Hi all, > Okay, I will prepare another patch which reverts the znver4 instruction > reservations and submit it. PFA the patch which reverts the znver4 instruction reservations. I have also made znver4 to use znver3 scheduler for now. If its good for the trunk, I will submit it.

RE: [PATCH] [X86_64]: Enable support for next generation AMD Zen4 CPU

[AMD Official Use Only - General] Hi, > I think it may make sense to make the initial patch without scheduler model > update with zen3 scheduling. I can work on updating the model which needs > some benchmarking and setting up > the cost tables first. > The problem here is that adding extra

RE: [PATCH] [X86_64]: Enable support for next generation AMD Zen4 CPU

[Public] Hi, > BTW: Perhaps znver1.md is not the right filename anymore, since it hosts all > four Zen schedulers. I have renamed the file to znver.md in this revision, PFA. Thank you for the review, we will push it for trunk if we don't get any further comments. Thanks and Regards, Tejas

[PATCH] [X86_64]: Enable support for next generation AMD Zen4 CPU

[Public] Hi all, PFA, the patch that enables support for the next generation AMD Zen4 CPU via -march=znver4. This is a basic enablement patch and as of now the costings, tunings are kept same as znver3. Good for trunk? Regards, Tejas