> -Original Message-
> From: Andrea Corallo
> Sent: 01 December 2020 13:52
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; nd
> Subject: [PATCH] arm: Improve documentation for effective target
> 'arm_softfloat'
>
> H
> -Original Message-
> From: Andrea Corallo
> Sent: 03 December 2020 17:14
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; nd
> Subject: [PATCH][GCC10][6/6] arm: Add vstN_lane_bf16 + vstNq_lane_bf16
> intrisics
>
> Hi all,
> -Original Message-
> From: Andrea Corallo
> Sent: 03 December 2020 17:13
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; nd
> Subject: [PATCH][GCC10][5/6] arm: Add vldN_lane_bf16 + vldNq_lane_bf16
> intrisics
>
> Hi all,
> -Original Message-
> From: Andrea Corallo
> Sent: 03 December 2020 17:11
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; nd
> Subject: [PATCH][GCC10][4/6] arm: Add vst1_bf16 + vst1q_bf16 intrinsics
>
> Hi all,
>
> fort
> -Original Message-
> From: Andrea Corallo
> Sent: 03 December 2020 17:10
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; nd
> Subject: [PATCH][GCC10][3/6] arm: Add vld1_bf16 + vld1q_bf16 intrinsics
>
> Hi all,
>
> thir
> -Original Message-
> From: Andrea Corallo
> Sent: 03 December 2020 17:09
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; nd
> Subject: [PATCH][GCC10][2/6] arm: Add vst1_lane_bf16 + vstq_lane_bf16
> intrinsics
>
> Hi all,
&
> -Original Message-
> From: Andrea Corallo
> Sent: 03 December 2020 17:08
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; nd
> Subject: [PATCH][GCC10][1/6] arm: Add vld1_lane_bf16 + vldq_lane_bf16
> intrinsics
>
> Hi all,
Hi Christophe,
From: Christophe Lyon
Sent: 10 December 2020 12:16
To: Kyrylo Tkachov
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH 1/5] arm: Auto-vectorization for MVE: vand
On Tue, 8 Dec 2020 at 15:00, Kyrylo Tkachov <mailto:kyrylo.tkac...@arm.com>
wrote:
> -Origina
> -Original Message-
> From: Gcc-patches On Behalf Of
> Richard Sandiford via Gcc-patches
> Sent: 10 December 2020 17:54
> To: Christophe Lyon
> Cc: Christophe Lyon via Gcc-patches
> Subject: Re: RFC: ARM MVE and Neon auto-vectorization
>
> Christophe Lyon writes:
> > On Wed, 9 Dec
> -Original Message-
> From: Tamar Christina
> Sent: 10 December 2020 17:00
> To: gcc-patches@gcc.gnu.org
> Cc: nd ; Ramana Radhakrishnan
> ; Richard Earnshaw
> ; ni...@redhat.com; Kyrylo Tkachov
>
> Subject: [PATCH]Arm: Add NEON and MVE RTL patterns for C
Hi all,
This patch extends the backend vector costs structures to allow for separate
Advanced SIMD and SVE
costs. The fields in the current cpu_vector_costs that would vary between the
ISAs are moved into
a simd_vec_cost struct and we have two typedefs of it: advsimd_vec_cost and
> -Original Message-
> From: Przemyslaw Wirkus
> Sent: 07 December 2020 21:20
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; Richard Sandiford
> ; Kyrylo Tkachov
> ; Marcus Shawcroft
>
> Subject: [PATCH][GCC] aarch64: Add +pauth to -mar
> -Original Message-
> From: Tamar Christina
> Sent: 25 September 2020 15:31
> To: gcc-patches@gcc.gnu.org
> Cc: nd ; Ramana Radhakrishnan
> ; Richard Earnshaw
> ; ni...@redhat.com; Kyrylo Tkachov
>
> Subject: [PATCH v2 13/16]Arm: Add support for auto-ve
> -Original Message-
> From: Christophe Lyon
> Sent: 08 December 2020 13:59
> To: Kyrylo Tkachov
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH 1/5] arm: Auto-vectorization for MVE: vand
>
> On Tue, 8 Dec 2020 at 14:19, Kyrylo Tkachov
> w
Hi Christophe
> -Original Message-
> From: Gcc-patches On Behalf Of
> Christophe Lyon via Gcc-patches
> Sent: 08 December 2020 13:06
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH 1/5] arm: Auto-vectorization for MVE: vand
>
> This patch enables MVE vandq instructions for
> -Original Message-
> From: Andrea Corallo
> Sent: 02 December 2020 16:06
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; nd
> Subject: [PATCH][GCC10] arm: Fix unwanted fall-through in arm.c
>
> Hi all,
>
> this is to fix
> -Original Message-
> From: Prathamesh Kulkarni
> Sent: 07 December 2020 11:26
> To: Kyrylo Tkachov
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PR66791][ARM] Replace calls to __builtin_neon_vmvn* by ~ for
> vmvn intrinsics
>
> On Mon, 7 Dec 2020 at 16:
Hi Prathamesh,
> -Original Message-
> From: Prathamesh Kulkarni
> Sent: 07 December 2020 11:01
> To: Kyrylo Tkachov
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PR66791][ARM] Replace calls to __builtin_neon_vmvn* by ~ for
> vmvn intrinsics
>
> On Thu,
Hi Prathamesh,
> -Original Message-
> From: Prathamesh Kulkarni
> Sent: 03 December 2020 10:50
> To: gcc Patches ; Kyrylo Tkachov
>
> Subject: [PR66791][ARM] Replace __builtin_neon_vcreate* for vcreate
> intrinsics
>
> Hi,
> This patch replaces calls to __
> -Original Message-
> From: Gcc-patches On Behalf Of
> Prathamesh Kulkarni via Gcc-patches
> Sent: 03 December 2020 10:30
> To: gcc Patches ; Kyrill Tkachov
>
> Subject: Re: [PR66791][ARM] Replace calls to __builtin_neon_vmvn* by ~ for
> vmvn intrinsics
>
> On Wed, 25 Nov 2020 at
> -Original Message-
> From: Richard Sandiford
> Sent: 27 November 2020 08:29
> To: Richard Biener
> Cc: Kyrylo Tkachov ; gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH] aarch64: Introduce --param=aarch64-autovec-
> preference to select autovec preference in backen
Hi all,
This is a patch that introduces the aarch64-autovec-preference that can take
values from 0 - 4, 0 being the default.
It can be used to override the autovectorisation preferences in the backend:
0 - use default scheme
1 - only use Advanced SIMD
2 - only use SVE
3 - use Advanced SIMD and
Hi Andrea,
> -Original Message-
> From: Andrea Corallo
> Sent: 26 November 2020 13:54
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; nd
> Subject: [PATCH] arm: [testsuite] fix lob tests for -mfloat-abi=hard
>
> Hi all,
>
>
> -Original Message-
> From: Stam Markianos-Wright
> Sent: 25 November 2020 13:49
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; Ramana
> Radhakrishnan ; Kyrylo Tkachov
> ; ni...@redhat.com
> Subject: [backport gcc-8,9][arm] Thumb2 out of range condition
> -Original Message-
> From: Matthew Malcomson
> Sent: 24 November 2020 16:20
> To: Kyrylo Tkachov
> Cc: Richard Sandiford ; gcc-
> patc...@gcc.gnu.org
> Subject: Re: libsanitizer: Hwasan reporting check for dladdr failing
>
> On 24/11/2020 15:53, Kyrylo Tk
Hi Matthew,
> -Original Message-
> From: Gcc-patches On Behalf Of
> Matthew Malcomson via Gcc-patches
> Sent: 24 November 2020 15:47
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Sandiford
> Subject: libsanitizer: Hwasan reporting check for dladdr failing
>
> Hello there,
>
> This is
> -Original Message-
> From: Gcc-patches On Behalf Of
> Christophe Lyon via Gcc-patches
> Sent: 23 November 2020 09:20
> To: gcc Patches
> Subject: testsuite/arm: add missing -mthumb to several tests
>
> Some tests force -mcpu=cortex-mXX but do not add -mthumb, causing
> errors if GCC
> -Original Message-
> From: Andrea Corallo
> Sent: 09 November 2020 18:24
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; nd ;
> christophe.l...@linaro.org
> Subject: [PATCH] [PR target/97727] aarch64: [testcase] fix
> bf16_v
> -Original Message-
> From: Jakub Jelinek
> Sent: 19 November 2020 18:57
> To: Richard Earnshaw ; Ramana
> Radhakrishnan ; Kyrylo Tkachov
>
> Cc: gcc-patches@gcc.gnu.org
> Subject: [PATCH] arm: Fix up neon_vector_mem_operand [PR97528]
>
> Hi!
>
&g
> -Original Message-
> From: Andrea Corallo
> Sent: 16 November 2020 16:11
> To: Andrea Corallo via Gcc-patches
> Cc: nd ; Richard Earnshaw ;
> Kyrylo Tkachov
> Subject: [PATCH] [PR target/97726] arm: [testsuite] fix some simd tests on
> armbe
>
>
> -Original Message-
> From: Tamar Christina
> Sent: 25 September 2020 15:30
> To: gcc-patches@gcc.gnu.org
> Cc: nd ; Richard Earnshaw ;
> Marcus Shawcroft ; Kyrylo Tkachov
> ; Richard Sandiford
>
> Subject: [PATCH v2 10/16]AArch64: Add NEON RTL patt
> -Original Message-
> From: Tamar Christina
> Sent: 25 September 2020 15:32
> To: gcc-patches@gcc.gnu.org
> Cc: nd ; Ramana Radhakrishnan
> ; Richard Earnshaw
> ; ni...@redhat.com; Kyrylo Tkachov
>
> Subject: [PATCH v2 15/16]Arm: Add MVE RTL patterns for C
> -Original Message-
> From: Tamar Christina
> Sent: 25 September 2020 15:31
> To: gcc-patches@gcc.gnu.org
> Cc: nd ; Ramana Radhakrishnan
> ; Richard Earnshaw
> ; ni...@redhat.com; Kyrylo Tkachov
>
> Subject: [PATCH v2 14/16]Arm: Add NEON RTL patterns for C
Hi Andrea,
> -Original Message-
> From: Andrea Corallo
> Sent: 10 November 2020 13:26
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; nd
> Subject: [PATCH] aarch64: Make use of RTL predicates
>
> Hi all,
>
> I'd like to prop
> -Original Message-
> From: Andrea Corallo
> Sent: 09 November 2020 10:04
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; nd
> Subject: [PATCH] aarch64: Do not alter force_reg returned register
> expanding fcmla
>
> Hi
> -Original Message-
> From: Andrea Corallo
> Sent: 09 November 2020 10:05
> To: Christophe Lyon
> Cc: Kyrylo Tkachov ; gcc-patches@gcc.gnu.org;
> Richard Earnshaw ; nd
> Subject: Re: [PATCH V2] arm: [testcase] Better narrow some bfloat16
> testcase
>
H, Christophe,
> -Original Message-
> From: Gcc-patches On Behalf Of
> Christophe Lyon via Gcc-patches
> Sent: 15 October 2020 18:23
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH] arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64
> intrinsics
>
> This patch adds implementations for
> -Original Message-
> From: Andrea Corallo
> Sent: 02 November 2020 09:04
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; nd
> Subject: [PATCH 6/x] arm: Add vstN_lane_bf16 + vstNq_lane_bf16 intrisics
>
> Hi all,
>
> las
HI Andrea,
> -Original Message-
> From: Andrea Corallo
> Sent: 02 November 2020 09:03
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; nd
> Subject: [PATCH 5/x] arm: Add vldN_lane_bf16 + vldNq_lane_bf16 intrisics
>
> Hi all,
>
> -Original Message-
> From: Andrea Corallo
> Sent: 02 November 2020 09:01
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; nd
> Subject: [PATCH 3/x] arm: Add vld1_bf16 + vld1q_bf16 intrinsics
>
> Hi all,
>
> Third patch o
> -Original Message-
> From: Andrea Corallo
> Sent: 03 November 2020 11:01
> To: Kyrylo Tkachov
> Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw
> ; nd
> Subject: Re: [PATCH 4/x] arm: Add vst1_bf16 + vst1q_bf16 intrinsics
>
> Kyrylo Tkachov writes:
> [
Hi Andrea,
> -Original Message-
> From: Andrea Corallo
> Sent: 02 November 2020 09:02
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; nd
> Subject: [PATCH 4/x] arm: Add vst1_bf16 + vst1q_bf16 intrinsics
>
> Hi all,
>
> For
Hi Andrea,
> -Original Message-
> From: Andrea Corallo
> Sent: 26 October 2020 16:02
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; nd
> Subject: [PATCH 2/x] arm: add vst1_lane_bf16 + vstq_lane_bf16 intrinsics
>
> Hi all,
>
&g
Hi Andrea,
> -Original Message-
> From: Andrea Corallo
> Sent: 26 October 2020 15:59
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; nd
> Subject: [PATCH 1/x] arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics
>
> Hi all,
>
>
> -Original Message-
> From: Jakub Jelinek
> Sent: 26 October 2020 09:32
> To: Kyrylo Tkachov
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH] PR tree-optimization/97546 Bail out of
> find_bswap_or_nop on non-INTEGER_CST sizes
>
> On Mon, Oct 26, 2020
Hi all,
This patch fixes the ICE in the PR by bailing out of find_bswap_or_nop on
poly_int sizes.
I don't think it intends to handle them and from my reading of the code it's
the most appropriate place to reject them
here rather than in the callers.
Bootstrapped and tested on
Hi Dennis,
> -Original Message-
> From: Dennis Zhang
> Sent: 06 October 2020 17:47
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; nd ;
> Richard Earnshaw ; Ramana Radhakrishnan
>
> Subject: Re: [PATCH][Arm] Auto-vectorization for MVE: vsub
>
> H
> -Original Message-
> From: Srinath Parvathaneni
> Sent: 16 October 2020 14:21
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov
> Subject: [PATCH][GCC] arm: Fix the warning -mcpu=cortex-m55 conflicting
> with -march=armv8.1-m.main (pr97327).
>
> H
> -Original Message-
> From: Srinath Parvathaneni
> Sent: 16 October 2020 12:45
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov
> Subject: [PATCH][GCC-10 backport] arm: [MVE] Remove illegal intrinsics (PR
> target/96914)
>
> Hello,
>
> Ap
> -Original Message-
> From: Srinath Parvathaneni
> Sent: 16 October 2020 12:45
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov
> Subject: [PATCH][GCC-10 backport] arm: [MVE] Add missing
> __arm_vcvtnq_u32_f32 intrinsic (PR 96914)
>
> Hell
> -Original Message-
> From: Srinath Parvathaneni
> Sent: 16 October 2020 12:45
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov
> Subject: [PATCH][GCC-10 backport] arm: [MVE] Add vqdmlashq intrinsics (PR
> target/96914)
>
> Hello,
>
> Ap
> -Original Message-
> From: Srinath Parvathaneni
> Sent: 07 October 2020 07:14
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov
> Subject: [PATCH][GCC] arm: Fix wrong code generated for mve scatter store
> with writeback intrinsics with -O2 (PR97271).
>
> -Original Message-
> From: Srinath Parvathaneni
> Sent: 06 October 2020 15:32
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov
> Subject: [PATCH][GCC-10 backport] arm: Add +nomve and +nomve.fp
> options to -mcpu=cortex-m55.
>
> Backport of
Hi Dennis,
> -Original Message-
> From: Dennis Zhang
> Sent: 06 October 2020 17:59
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; nd ;
> Richard Earnshaw ; Ramana Radhakrishnan
>
> Subject: [PATCH][Arm] Auto-vectorization for MVE: vmin/vmax
>
> Hi al
Hi Dennis,
> -Original Message-
> From: Dennis Zhang
> Sent: 06 October 2020 17:55
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; nd ;
> Richard Earnshaw ; Ramana Radhakrishnan
>
> Subject: [PATCH][Arm] Auto-vectorization for MVE: vmul
>
> Hi all,
&g
Hi all,
This is the GCC 8 patch for the Neoverse N2 tuning struct.
It sets the AARCH64_EXTRA_TUNE_PREFER_ADVSIMD_AUTOVEC tune flag as well.
Bootstrapped and tested on the branch.
Pushing to GCC 8.
Thanks,
Kyrill
gcc/
* config/aarch64/aarch64.c (neoversen2_tunings): Define.
*
Hi all,
This is the GCC 9 patch for the Neoverse N2 tuning struct.
It sets the AARCH64_EXTRA_TUNE_PREFER_ADVSIMD_AUTOVEC tune flag as well.
Bootstrapped and tested on the branch.
Pushing to GCC 9.
Thanks,
Kyrill
gcc/
* config/aarch64/aarch64.c (neoversen2_tunings): Define.
*
This is the GCC 10 version of the Neoverse N2 tuning struct patch.
It's more or less identical.
Bootstrapped and tested on the branch.
Pushing to GCC 10.
Thanks,
Kyrill
gcc/
* config/aarch64/aarch64.c (neoversen2_tunings): Define.
* config/aarch64/aarch64-cores.def (neoverse-n2):
Hi all,
This patch adds a tuning structure for Neoverse N2 to allow for further tuning.
For now it's just a deduplication of the Neoverse N1 struct that it was reusing
but with the SVE width set to 128.
Bootstrapped and tested on aarch64-none-linux-gnu.
Pushing to trunk and will push similar
> -Original Message-
> From: Przemyslaw Wirkus
> Sent: 13 October 2020 10:56
> To: gcc-patches@gcc.gnu.org
> Cc: ni...@redhat.com; Richard Earnshaw ;
> Kyrylo Tkachov ; Ramana Radhakrishnan
>
> Subject: [PATCH][GCC-10 backport] arm: Fix fp16 move patterns for
> -Original Message-
> From: Przemyslaw Wirkus
> Sent: 13 October 2020 10:56
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; ni...@redhat.com;
> Ramana Radhakrishnan ; Kyrylo
> Tkachov
> Subject: [PATCH][GCC-10 backport] arm: Fix ICEs in no-literal-
Hi Christophe,
> -Original Message-
> From: Gcc-patches On Behalf Of
> Christophe Lyon via Gcc-patches
> Sent: 12 October 2020 12:41
> To: Dennis Zhang
> Cc: Richard Earnshaw ; nd ;
> gcc-patches@gcc.gnu.org; Ramana Radhakrishnan
>
> Subject: Re: Ping: [PATCH][Arm] Enable MVE SIMD
Hi all,
This patch fixes the PR by adjusting the input types of the intrinsic
prototypes to the ones mandated by ACLE
Turns out the tests in the testsuite were already using the correct ones, but
implicit conversions hid the bug...
Bootstrapped and tested on aarch64-none-linux-gnu.
Pushing to
Hi all,
I'd like to backport this patch to the GCC 9 branch to implement these
Armv8.5-a intrinsics that should have been there.
The backport is fairly simple.
Bootstrapped and tested on aarch64-none-linux-gnu.
Pushing to GCC 9 branch.
This patch implements the ACLE intrinsics to access the
> -Original Message-
> From: Gcc-patches On Behalf Of
> Christophe Lyon via Gcc-patches
> Sent: 05 October 2020 10:58
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH] arm: [MVE] Add missing __arm_vcvtnq_u32_f32 intrinsic
> (PR 96914)
>
> __arm_vcvtnq_u32_f32 was missing from
Hi Christophe
> -Original Message-
> From: Gcc-patches On Behalf Of
> Christophe Lyon via Gcc-patches
> Sent: 06 October 2020 16:59
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH v2] arm: [MVE[ Add vqdmlashq intrinsics
>
> This patch adds:
> vqdmlashq_m_n_s16
> vqdmlashq_m_n_s32
>
With gcc-patches on too.
Not sure why the reply-all function fails for your address
Kyrill
> -Original Message-
> From: Kyrylo Tkachov
> Sent: 06 October 2020 17:13
> To: Christophe Lyon
> Subject: RE: [PATCH v2] arm: [MVE] Remove illegal intrinsics
>
>
>
&
> -Original Message-
> From: Srinath Parvathaneni
> Sent: 06 October 2020 14:55
> To: Kyrylo Tkachov ; gcc-patches@gcc.gnu.org
> Subject: RE: [PATCH][GCC] arm: Move iterators from mve.md to iterators.md
> to maintain consistency.
>
> Hi Kyrill,
>
Hi Dennis,
> -Original Message-
> From: Dennis Zhang
> Sent: 06 October 2020 14:37
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; nd ;
> Richard Earnshaw ; Ramana Radhakrishnan
>
> Subject: Ping: [PATCH][Arm] Enable MVE SIMD modes for vectorization
>
&
> -Original Message-
> From: Srinath Parvathaneni
> Sent: 06 October 2020 13:27
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov
> Subject: [PATCH][GCC] arm: Move iterators from mve.md to iterators.md to
> maintain consistency.
>
> Hello,
>
> To ma
> -Original Message-
> From: Srinath Parvathaneni
> Sent: 06 October 2020 14:37
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov
> Subject: [PATCH][GCC-10 backport] arm: Remove coercion from scalar
> argument to vmin & vmax intrinsics.
>
> Hello,
> -Original Message-
> From: Alex Coplan
> Sent: 02 October 2020 15:49
> To: gcc-patches@gcc.gnu.org
> Cc: ni...@redhat.com; Richard Earnshaw ;
> Ramana Radhakrishnan ; Kyrylo
> Tkachov
> Subject: [PATCH][GCC 10] arm: Add support for Neoverse N2 CPU
&
> -Original Message-
> From: Alex Coplan
> Sent: 02 October 2020 15:41
> To: gcc-patches@gcc.gnu.org
> Cc: ni...@redhat.com; Richard Earnshaw ;
> Ramana Radhakrishnan ; Kyrylo
> Tkachov
> Subject: [PATCH] arm: Add missing part number for Neoverse V1
>
> T
Hi all,
This GCC 8 patch duplicates the Cortex-A72 tuning struct that's currently used
for Neoverse V1 and AARCH64_EXTRA_TUNE_PREFER_ADVSIMD_AUTOVEC tune flag to
prefer Advanced SIMD over SVE autovectorisation.
Bootstrapped and tested on GCC 8, pushing to the branch.
Thanks,
Kyrill
gcc/
Hi all,
This GCC 9 patch duplicates the Neoverse N1 tuning struct that's currently used
for Neoverse V1 and AARCH64_EXTRA_TUNE_PREFER_ADVSIMD_AUTOVEC tune flag to
prefer Advanced SIMD over SVE autovectorisation.
Bootstrapped and tested on GCC 9, pushing to the branch.
Thanks,
Kyrill
gcc/
Hi all,
This patch adds a Neoverse V1-specific tuning struct that currently is just a
deduplication of the N1 struct it was using before and specifying the SVE width.
This will allow us to tweak Neoverse V1 things in the future as needed.
Bootstrapped and tested on aarch64-none-linux-gnu.
Hi Joe,
> -Original Message-
> From: Gcc-patches On Behalf Of Joe
> Ramsay
> Sent: 19 August 2020 17:12
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH v2][GCC] arm: Add +nomve and +nomve.fp options to -
> mcpu=cortex-m55
>
> From: Joe Ramsay
>
> Hi all,
>
> This patch rearranges
Hi Joe,
> -Original Message-
> From: Gcc-patches On Behalf Of Joe
> Ramsay
> Sent: 13 August 2020 14:16
> To: Joe Ramsay ; gcc-patches@gcc.gnu.org
> Subject: [PATCH] arm: Remove coercion from scalar argument to vmin &
> vmax intrinsics
>
> From: Joe Ramsay
>
> Hi,
>
> This patch
> -Original Message-
> From: Richard Sandiford
> Sent: 02 October 2020 11:39
> To: Christophe Lyon
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> ; Dennis Zhang ;
> gcc-patches@gcc.gnu.org; Ramana Radhakrishnan
>
> Subject: [PATCH] arm: Make more use of the new
Hi all,
I'd like to add a prefer_advsimd_autovec internal tune_flag that makes GCC pick
Advanced SIMD over SVE for autovectorisation.
No CPU tuning uses it yet, but I'd like to add this to the GCC 8 and 9 branches
only as SVE autovectorisation is less mature there and CPUs
may want to prefer
Hi Richard,
> -Original Message-
> From: Richard Sandiford
> Sent: 01 October 2020 15:10
> To: gcc-patches@gcc.gnu.org
> Cc: ni...@redhat.com; Richard Earnshaw ;
> Ramana Radhakrishnan ; Kyrylo
> Tkachov
> Subject: [PATCH] arm: Add missing vec_cmp and vcond patte
> -Original Message-
> From: Andrea Corallo
> Sent: 01 October 2020 15:36
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; Kyrylo Tkachov
> ; Christophe Lyon
> Subject: Re: [PATCH PR96375] arm: Fix testcase selection for Low Overhead
> Loop tests
>
Hi all,
This patch adds the +rng feature to the Neoverse V1 entry. It exists in the GCC
11 and 10 branches, but was missed out on GCC 9 and 8 as those didn't support
the rng intrinsic then, but they do now.
Bootstrapped and tested on aarch64-none-linux-gnu.
Committing to GCC 8.
Thanks,
Kyrill
Hi all,
This patch adds the +rng feature to the Neoverse V1 entry. It exists in the GCC
11 and 10 branches, but was missed out on GCC 9 and 8 as those didn't support
the rng intrinsic then, but they do now.
Bootstrapped and tested on aarch64-none-linux-gnu.
Committing to GCC 9 and an
> -Original Message-
> From: Alex Coplan
> Sent: 01 October 2020 09:28
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; Richard Sandiford
> ; Kyrylo Tkachov
> Subject: [PATCH][GCC 8] aarch64: Add support for Neoverse N2 CPU
>
> This patch backports th
> -Original Message-
> From: Alex Coplan
> Sent: 01 October 2020 09:25
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; Richard Sandiford
> ; Kyrylo Tkachov
> Subject: [PATCH][GCC 9] aarch64: Add support for Neoverse N2 CPU
>
> This patch backports th
Now adding gcc-patches too
> -Original Message-
> From: Kyrylo Tkachov
> Sent: 30 September 2020 15:02
> To: Christophe Lyon
> Subject: RE: [PATCH 1/1] arm: [testsuite] Skip thumb2-cond-cmp tests on
> Cortex-M [PR94595]
>
> Hi Christophe,
>
> > -Or
Hi Srinath,
> -Original Message-
> From: Srinath Parvathaneni
> Sent: 30 September 2020 12:51
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov
> Subject: [GCC][PATCH] arm: Fix MVE intrinsics polymorphic variants wrongly
> generating __ARM_undef type
> -Original Message-
> From: Przemyslaw Wirkus
> Sent: 30 September 2020 11:39
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; Richard Sandiford
> ; Kyrylo Tkachov
> ; Marcus Shawcroft
>
> Subject: [PATCH][GCC][AArch64] Add support for Cor
> -Original Message-
> From: Przemyslaw Wirkus
> Sent: 30 September 2020 11:42
> To: gcc-patches@gcc.gnu.org
> Cc: ni...@redhat.com; Ramana Radhakrishnan
> ; Kyrylo Tkachov
> ; Richard Earnshaw
>
> Subject: [PATCH][GCC][ARM] Add support for Cortex-A78 and C
Hi all,
In this PR we have the wrong return type for some intrinsics. It should be
unsigned, but we implement it as signed.
Fix this by adjusting the type qualifiers used when creating the builtins and
fixing the type in the arm_neon.h intrinsic.
With the adjustment in qualifiers we now don't
Hi all,
In this PR the second argument to the intrinsics should be signed but we use an
unsigned one erroneously.
The corresponding builtins are already using the correct types so it's just a
matter of correcting the signatures
in arm_neon.h
Bootstrapped and tested on aarch64-none-linux-gnu.
Hi Alex,
> -Original Message-
> From: Alex Coplan
> Sent: 29 September 2020 14:48
> To: gcc-patches@gcc.gnu.org
> Cc: ni...@redhat.com; Richard Earnshaw ;
> Ramana Radhakrishnan ; Kyrylo
> Tkachov
> Subject: [PATCH] arm: Fix ICEs in no-literal-pool.c on MVE
>
From: Przemyslaw Wirkus
Sent: 29 September 2020 15:43
To: gcc-patches@gcc.gnu.org
Cc: ni...@redhat.com; Ramana Radhakrishnan ;
Richard Earnshaw ; Kyrylo Tkachov
Subject: [PATCH][GCC][ARM] Add support for Cortex-X1
Hi,
This change adds support for the Arm Cortex-X1 CPU. For more
> -Original Message-
> From: Przemyslaw Wirkus
> Sent: 29 September 2020 15:39
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; Richard Sandiford
> ; Kyrylo Tkachov
> ; Marcus Shawcroft
>
> Subject: [PATCH][GCC][AArch64] Add support for Cortex-X1
>
> -Original Message-
> From: Alex Coplan
> Sent: 29 September 2020 17:04
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; Richard Sandiford
> ; Kyrylo Tkachov
> Subject: [PATCH][GCC 10] aarch64: Add support for Neoverse N2 CPU
>
> Hello,
>
>
> -Original Message-
> From: Alex Coplan
> Sent: 29 September 2020 13:17
> To: gcc-patches@gcc.gnu.org
> Cc: ni...@redhat.com; Richard Earnshaw ;
> Ramana Radhakrishnan ; Kyrylo
> Tkachov
> Subject: [PATCH][GCC 8] arm: Add support for Neoverse V1 CPU
>
> -Original Message-
> From: Richard Sandiford
> Sent: 29 September 2020 11:27
> To: Kyrylo Tkachov
> Cc: gcc-patches@gcc.gnu.org; ni...@redhat.com; Richard Earnshaw
> ; Ramana Radhakrishnan
> ; Dennis Zhang
>
> Subject: Ping: [PATCH] arm: Add new v
> -Original Message-
> From: Alex Coplan
> Sent: 29 September 2020 11:18
> To: gcc-patches@gcc.gnu.org
> Cc: ni...@redhat.com; Richard Earnshaw ;
> Ramana Radhakrishnan ; Kyrylo
> Tkachov
> Subject: [PATCH][GCC 9] arm: Add support for Neoverse V1 CPU
>
> -Original Message-
> From: Alex Coplan
> Sent: 29 September 2020 09:59
> To: gcc-patches@gcc.gnu.org
> Cc: ni...@redhat.com; Richard Earnshaw ;
> Ramana Radhakrishnan ; Kyrylo
> Tkachov
> Subject: [PATCH][GCC 10] arm: Add support for Neoverse V1 CPU
>
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