Hi Kyrill,
On 02/27/2020 11:09 AM, Kyrill Tkachov wrote:
Hi Mihail,
On 2/27/20 10:27 AM, Mihail Ionescu wrote:
Hi,
This patch adds support for the bf16 vector create, get, set,
duplicate and reinterpret intrinsics.
ACLE documents are at https://developer.arm.com/docs/101028/latest
ISA
diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index
09297831cdcd6e695843c17b7724c114f3a129fe..5901a8f1fb84f204ae95f0ccc97bf5ae944c482c
100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -42,6 +42,15 @@ extern "C" {
#include
#include
+#ifdef __ARM_
Hi,
On 02/17/2020 05:53 PM, Mihail Ionescu wrote:
Hi,
This patch adds support for the bf16 duplicate and reinterpret intrinsics.
ACLE documents are at https://developer.arm.com/docs/101028/latest
ISA documents are at https://developer.arm.com/docs/ddi0596/latest
Regression tested on aarch64
);
|
^~~
| |
| const __bf16*
I think the affected lines are:
Mihail Ionescu writes:
+__extension__ extern __inline bfloat16x4x2_t
the same behaviour is
achieved during
code generation by using the new instructions[1].
[1] https://gcc.gnu.org/ml/gcc-patches/2019-10/msg01654.html
Tested on arm-none-eabi.
gcc/ChangeLog:
2020-02-20 Mihail Ionescu
* config/arm/t-rmprofile: create new multilib for
armv8.1-m.main
Hi Christophe,
On 01/23/2020 09:34 AM, Christophe Lyon wrote:
On Mon, 20 Jan 2020 at 19:01, Mihail Ionescu
wrote:
Hi,
This patch fixes the scalar shifts tests added in:
https://gcc.gnu.org/ml/gcc-patches/2019-11/msg01195.html
https://gcc.gnu.org/ml/gcc-patches/2019-11/msg01196.html
By
:
2020-02-17 Mihail Ionescu
* config/aarch64/aarch64-builtins.c (aarch64_scalar_builtin_types):
Add simd_bf.
(aarch64_init_simd_builtin_scalar_types): Register simd_bf.
(VAR14, VAR15): New.
* config/aarch64/iterators.md
(VDC): Enable for V4BF and
:
2020-02-17 Mihail Ionescu
* config/aarch64/iterators.md (VDQF_F16) Add V4BF and V8BF.
(VALL_F16): Likewise.
(VALLDI_F16): Likewise.
(Vtype): Likewise.
(Vetype): Likewise.
(vswap_width_name): Likewise.
(VSWAP_WIDTH): Likewise.
(Vel
Hi all,
I've regenerated arm-tables.opt in config/arm to replace the improperly
generated arm-tables.opt file from "[PATCH, GCC/ARM, 2/10] Add command
line support for Armv8.1-M Mainline" (9722215a027b68651c3c7a8af9204d033197e9c0).
2020-02-03 Mihail Ionescu
* config/arm
Hi,
We noticed that the profile for armv8.1-m.main was not set in arm-cpus.in
, which led to TARGET_ARM_ARCH_PROFILE and _ARM_ARCH_PROFILE not being
defined properly.
gcc/ChangeLog:
2020-02-03 Mihail Ionescu
* config/arm/arm-cpus.in: Set profile M
for armv8.1-m.main.
Ok
Hi,
This patch fixes the uninitialised 'last_regno' variable introduced in:
https://gcc.gnu.org/ml/gcc-patches/2019-12/msg01299.html
and makes the clear_operation_p code more readable.
*** gcc/ChangeLog ***
2020-01-20 Mihail-Calin Ionescu
* gcc/config/arm/arm.c (clear_operation_p):
Hi Christophe,
On 01/20/2020 01:19 PM, Christophe Lyon wrote:
On Thu, 14 Nov 2019 at 15:19, Mihail Ionescu
wrote:
Hi,
This is part of a series of patches where I am trying to add new
instructions for Armv8.1-M Mainline to the arm backend.
This patch is adding the following instructions
Hi,
This patch fixes the scalar shifts tests added in:
https://gcc.gnu.org/ml/gcc-patches/2019-11/msg01195.html
https://gcc.gnu.org/ml/gcc-patches/2019-11/msg01196.html
By adding mthumb and ensuring that the target supports
thumb2 instructions.
*** gcc/testsuite/ChangeLog ***
2020-01-20 Mihail
Hi Jakub,
On 01/17/2020 08:37 AM, Jakub Jelinek wrote:
On Wed, Dec 18, 2019 at 05:00:01PM +, Mihail Ionescu wrote:
2019-12-18 Mihail Ionescu
2019-12-18 Andre Vieira
* config/arm/arm-cpus.in (mve, mve_float): New features.
(dsp, mve, mve.fp): New options.
Note, the
Hi Kyrill,
On 12/18/2019 02:13 PM, Kyrill Tkachov wrote:
Hi Mihail,
On 11/8/19 4:52 PM, Mihail Ionescu wrote:
Hi,
This patch adds CLI and multilib support for Armv8.1-M MVE to the Arm
backend.
Two new option added for v8.1-m.main: "+mve" for integer MVE
instructions only
and &qu
Hi,
On 11/12/2019 10:23 AM, Kyrill Tkachov wrote:
On 10/23/19 10:26 AM, Mihail Ionescu wrote:
[PATCH, GCC/ARM, 9/10] Call nscall function with blxns
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline Security Extensions architecture. Its purpose
Hi Kyrill,
On 11/12/2019 10:22 AM, Kyrill Tkachov wrote:
Hi Mihail,
On 10/23/19 3:24 PM, Mihail Ionescu wrote:
[PATCH, GCC/ARM, 8/10] Do lazy store & load inline when calling nscall
function
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Main
Hi Kyrill,
On 12/17/2019 10:26 AM, Kyrill Tkachov wrote:
Hi Mihail,
On 12/16/19 6:29 PM, Mihail Ionescu wrote:
Hi Kyrill,
On 11/12/2019 09:55 AM, Kyrill Tkachov wrote:
Hi Mihail,
On 10/23/19 10:26 AM, Mihail Ionescu wrote:
[PATCH, GCC/ARM, 4/10] Clear GPR with CLRM
Hi,
=== Context
Hi Kyrill,
On 12/11/2019 05:50 PM, Kyrill Tkachov wrote:
Hi Mihail,
On 11/14/19 1:54 PM, Mihail Ionescu wrote:
Hi,
This patch adds the new scalar shift instructions for Armv8.1-M
Mainline to the arm backend.
This patch is adding the following instructions:
ASRL (reg)
LSLL (reg)
Sorry
Hi all,
I have committed the attached patch adding myself to the Write After
Approval section of the MAINTAINERS file.
ChangeLog:
2019-12-17 Mihail Ionescu
* MAINTAINERS (write_after_approval): Add myself.
Regards,
Mihail
diff --git a/MAINTAINERS b/MAINTAINERS
index
Hi Kyrill,
On 11/12/2019 09:55 AM, Kyrill Tkachov wrote:
Hi Mihail,
On 10/23/19 10:26 AM, Mihail Ionescu wrote:
[PATCH, GCC/ARM, 4/10] Clear GPR with CLRM
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline Security Extensions architecture. Its
Hi Kyrill,
On 11/06/2019 04:12 PM, Kyrill Tkachov wrote:
Hi Mihail,
On 10/23/19 10:26 AM, Mihail Ionescu wrote:
[PATCH, GCC/ARM, 3/10] Save/restore FPCXTNS in nsentry functions
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline Security
Hi Kyrill
On 11/06/2019 03:59 PM, Kyrill Tkachov wrote:
Hi Mihail,
On 11/4/19 4:49 PM, Kyrill Tkachov wrote:
Hi Mihail,
On 10/23/19 10:26 AM, Mihail Ionescu wrote:
> [PATCH, GCC/ARM, 2/10] Add command line support
>
> Hi,
>
> === Context ===
>
> This patch is part of
Hi,
This is part of a series of patches where I am trying to add new
instructions for Armv8.1-M Mainline to the arm backend.
This patch is adding the following instructions:
ASRL (imm)
LSLL (imm)
LSRL (imm)
ChangeLog entry are as follow:
*** gcc/ChangeLog ***
2019-11-14 Mihail-Calin Ionescu
Hi,
This patch adds the new scalar shift instructions for Armv8.1-M
Mainline to the arm backend.
This patch is adding the following instructions:
ASRL (reg)
LSLL (reg)
ChangeLog entry are as follow:
*** gcc/ChangeLog ***
2019-11-14 Mihail-Calin Ionescu
2019-11-14 Sudakshina Das
Hi,
This is a patch series to introduce the Armv8.1-M Mainline scalar shift
instructions to the arm backend.
Mihail Ionescu (2)
[PATCH, GCC/ARM, 1/2] Add support for ASRL(reg) and LSLL(reg) instructions for
Armv8.1-M Mainline
[PATCH, GCC/ARM, 2/2] Add support for ASRL(imm), LSLL(imm) and LSRL
e Armv8.1-M multilib variants to the corresponding v8-M
ones.
gcc/ChangeLog:
2019-11-08 Mihail Ionescu
2019-11-08 Andre Vieira
* config/arm/arm-cpus.in (mve, mve_float): New features.
(dsp, mve, mve.fp): New options.
* config/arm/arm.h (TARGET_HAVE_MVE, TARGET_HAV
[PATCH, GCC/ARM, 9/10] Call nscall function with blxns
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline Security Extensions architecture. Its purpose is to call
functions with the cmse_nonsecure_call attribute directly using blxns
with no undue restr
[PATCH, GCC/ARM, 2/10] Add command line support
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline Security Extensions architecture. Its purpose is to add
command-line support for that new architecture.
=== Patch description ===
Besides the expected
[PATCH, GCC/ARM, 3/10] Save/restore FPCXTNS in nsentry functions
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline Security Extensions architecture. Its purpose is to enable
saving/restoring of nonsecure FP context in function with the
cmse_nonsecure_
[PATCH, GCC/ARM, 4/10] Clear GPR with CLRM
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline Security Extensions architecture. Its purpose is to improve
code density of functions with the cmse_nonsecure_entry attribute and
when calling function with t
[PATCH, GCC/ARM, 6/10] Clear GPRs inline when calling nscall function
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline Security Extensions architecture. Its purpose is to generate
inline callee-saved register clearing when calling a function with the
[PATCH, GCC/ARM, 8/10] Do lazy store & load inline when calling nscall function
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline Security Extensions architecture. Its purpose is to generate
lazy store and load instruction inline when calling a functi
[PATCH, GCC/ARM, 1/10] Fix -mcmse check in libgcc
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline Security Extensions architecture. Its purpose is to fix the
check to determine whether -mcmse is supported by the host compiler.
=== Patch description
[PATCH, GCC/ARM, 5/10] Clear VFP registers with VSCCLRM
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline Security Extensions architecture. Its purpose is to improve
code density of functions with the cmse_nonsecure_entry attribute and
when calling fu
[PATCH, GCC/ARM, 7/10] Clear all VFP regs inline in hardfloat nscall functions
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline Security Extensions architecture. Its purpose is to generate
inline instructions to save, clear and restore callee-saved V
[PATCH, GCC/ARM, 10/10] Enable -mcmse
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline Security Extensions architecture. Its purpose is to enable the
-mcmse option now that support for Armv8.1-M Security Extension is
complete.
=== Patch description
This is a patch series to implement support for the Armv8.1-M Mainline Security
Extensions. The specification can be found in:
https://developer.arm.com/docs/ddi0553/latest
Mihail Ionescu(10)
[PATCH, GCC/ARM, 1/10] Fix -mcmse check in libgcc
[PATCH, GCC/ARM, 2/10] Add command line support for
Hi,
I previously did not properly attach the diff.
Regards,
Mihail
On 10/22/2019 05:06 PM, Mihail Ionescu wrote:
Hi,
This is a backport from trunk for GCC9.
SVN revision: r277156.
Built and tested on arm-none-eabi (comparted
-march=armv7e-m+fp/-mfloat-abi=hard
to -march=armv7-r+fp.sp
Hi,
This is a backport from trunk for GCC9.
SVN revision: r277156.
Built and tested on arm-none-eabi (comparted
-march=armv7e-m+fp/-mfloat-abi=hard
to -march=armv7-r+fp.sp/-mfloat-abi=hard).
gcc/ChangeLog:
2019-10-21 Mihail Ionescu
Backport from mainline
2019-10-18
Ping?
Best regards,
Mihail
On 12/18/2018 12:53 PM, Mihail Ionescu wrote:
On 12/18/2018 09:32 AM, Mihail Ionescu wrote:
Hi All,
In Thumb mode when the function prologue gets expanded, in case of a
multiple register push, additional mov instructions are generated to
save the high
On 12/18/2018 09:32 AM, Mihail Ionescu wrote:
Hi All,
In Thumb mode when the function prologue gets expanded, in case of a
multiple register push, additional mov instructions are generated to
save the high registers which result in lr getting overwritten before
it's value can be us
ts of detecting if lr is alive after the prologue, in
which case, the lr register won't be used as a scratch.
Regression tested on arm-none-eabi.
gcc/ChangeLog:
2018-11-23 Mihail Ionescu
PR target/88167
* config/arm/arm.c: Add lr liveness check.
gcc/testsuite/ChangeLog
Ping?
Best regards,
Mihail
On 11/07/2018 05:46 PM, Mihail Ionescu wrote:
On 10/09/2018 09:52 AM, Ramana Radhakrishnan wrote:
On 09/10/2018 09:27, Mihail Ionescu wrote:
Hi all,
This patch removes some of the machine mode checks from the arm
backend when
emitting instructions by using the
Hi Sudi
On 11/08/2018 06:53 PM, Sudakshina Das wrote:
Hi Mihail
On 08/11/18 10:02, Ramana Radhakrishnan wrote:
On 07/11/2018 17:49, Mihail Ionescu wrote:
Hi All,
This is a backport from trunk for GCC 8 and 7.
SVN revision: r264595.
Regression tested on arm-none-eabi.
gcc/ChangeLog
2018
Hi All,
This is a backport from trunk for GCC 8 and 7.
SVN revision: r264595.
Regression tested on arm-none-eabi.
gcc/ChangeLog
2018-11-02 Mihail Ionescu
Backport from mainiline
2018-09-26 Eric Botcazou
* config/arm/arm.c (arm_reorg): Skip Thumb reorg pass
On 10/09/2018 09:52 AM, Ramana Radhakrishnan wrote:
On 09/10/2018 09:27, Mihail Ionescu wrote:
Hi all,
This patch removes some of the machine mode checks from the arm backend when
emitting instructions by using the '@' construct (Parameterized Names[2]). It
is based on the previo
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