Re: [PATCH 1/1] [V2] [RISC-V] support cm.push cm.pop cm.popret in zcmp

>> +/* Return TRUE if Zcmp push and pop insns should be >> + avoided. FALSE otherwise. >> + Only use multi push & pop if all GPRs masked can be covered, >> + and stack access is SP based, >> + and GPRs are at top of the stack frame, >> + and no conflicts in stack allocation with other features */ >

Re: [PATCH 4/5] RISC-V: Add Zcmp extension supports.

Hi, Kito and Jiawei I have noticed several comments are not accurate or no longer valid(e.g. only for zc 0.5) and they need an update or improvement. > + >> +namespace { >> + >> +/* >> + 1. preprocessing: >> + 1.1. if there is no push rtx, then just return. e.g. >> + (note 5 1 22 2 [bb 2] NOTE_INS

Re: Re: [PATCH 4/5] RISC-V: Add Zcmp extension supports.

Hi Fei, Sorry for the late reply, I've been busy with moving these days :(. Thanks for working on it. I would prefer removing the extra pass for popretz if possible ... I will test your patches ASAP. BR, Sinan -- Sender:Fei Gao Sent

Re: [PATCH 4/5] RISC-V: Add Zcmp extension supports.

> hi Jiawei > > Please ignore my previous reply. I accidently sent the email before I > finished it. > Sorry for that! > > I downloaded the series of patches from you and found in some cases > it fails to generate zcmp push and pop insns. > > TC: > > char my_getchar(); > int test_s0() > { > >

[PATCH] RISC-V: add TARGET_ZBKB to the condition of bswapsi2, bswapdi2 and rotr3 patterns

From: Sinan Lin tell gcc that zbkb has these two spn to enable some optimizations. e.g. 1) the rrotate_expr could match to rotrm3 during expand; 2) hook up __builtin_bswap64 with `rev8` in zbkb64. --- gcc/config/riscv/bitmanip.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff

[PATCH] RISC-V: avoid splitting small constant in i_extrabit pattern

From: Sinan Lin there is no need to split an xori/ori with an small constant. take the test case `int foo(int idx) { return idx|3; }` as an example, rv64im_zba generates: ori a0,a0,3 ret but, rv64im_zba_zbs generates: ori a0,a0,1 ori a0,a0,2 re

[PATCH] RISC-V: Fix wrong partial subreg check for bsetidisi

From: Lin Sinan The partial subreg check should be for subreg operand(operand 1) instead of the immediate operand(operand 2). This change also fix pr68648.c in zbs. gcc/ChangeLog: * config/riscv/bitmanip.md: Fix wrong index in the check. --- gcc/config/riscv/bitmanip.md | 2 +- 1 file

[PATCH] RISC-V: Allow const0_rtx operand in max/min

From 73e743348a49a7fffcf2e328b8179e8dbbc3b2b4 Mon Sep 17 00:00:00 2001 From: Lin Sinan Date: Tue, 28 Feb 2023 00:44:55 +0800 Subject: [PATCH] RISC-V: Allow const0_rtx operand in max/min Optimize cases that use max[u]/min[u] against a zero constant. E.g., the case int f(int x) { return x >= 0 ? x :

Re: [PING] [PATCH RESEND] riscv: improve the cost model for loading a 64bit constant in rv32.

> The motivation of this patch is to correct the wrong estimation of >> the number of instructions needed for loading a 64bit constant in >> rv32 in the current cost model(riscv_interger_cost). According to >> the current implementation, if a constant requires more than 3 >> instructions(riscv_cons

[PATCH RESEND] riscv: improve the cost model for loading a 64bit constant in rv32.

The motivation of this patch is to correct the wrong estimation of the number of instructions needed for loading a 64bit constant in rv32 in the current cost model(riscv_interger_cost). According to the current implementation, if a constant requires more than 3 instructions(riscv_const_insn and

RE: [PATCH] RISC-V: cost model for loading 64bit constant in rv32

>> comparison with clang: >> https://godbolt.org/z/v5nxTbKe9 > > IIUC the rules are generally no compiler explorer links (so we can > preserve history) and no attachment patches (ie, inline them like > git-send-email does). There's some documenation on sending pat

[PATCH] Fix doc typo

add a missing variable name. 0001-doc-FixDocTypo.patch Description: Binary data

[PATCH] RISC-V: cost model for loading 64bit constant in rv32

loading constant 0x739290001LL in rv32 can be done with three instructions output: li a1, 7 lui a1, 234128 addi a1, a1, 1 Similarly, loading 0x839290001LL in rv32 can be done within three instructions expected output: li a1, 8 lui a1, 234128 addi a1, a1, 1 However, riscv_build_integer does not hand