Hi all,
On 28/09/2023 13:51, Andre Vieira (lists) wrote:
Hi,
On 14/09/2023 13:10, Kyrylo Tkachov via Gcc-patches wrote:
Hi Stam,
The arm parts look sensible but we'd need review for the df-core.h
and df-core.cc changes.
Maybe Jeff can help or can recommend someone to take a look?
Just
On 06/11/2023 11:24, Richard Sandiford wrote:
Stamatis Markianos-Wright writes:
One of the main reasons for reading the arm bits was to try to answer
the question: if we switch to a downcounting loop with a GE condition,
how do we make sure that the start value is not a large unsigned
number
Pinging back to the top of reviewers' inboxes due to worry about Stage 1
End in a few days :)
See the last email for the latest version of the 2/2 patch. The 1/2
patch is A-Ok from Kyrill's earlier target-backend review.
On 10/11/2023 12:41, Stamatis Markianos-Wright wrote:
On
x27;s fastmodels.
Ok for trunk?
Thanks,
Stamatis Markianos-Wright
gcc/ChangeLog:
* config/arm/arm-mve-builtins-base.cc (vcaddq_rot90, vcaddq_rot270):
Use common insn for signed and unsigned front-end definitions.
* config/arm/arm_mve_builtins.def
(vcaddq_rot90_m_u, vcaddq_rot27
Hi all,
This is the 2/2 patch that contains the functional changes needed
for MVE Tail Predicated Low Overhead Loops. See my previous email
for a general introduction of MVE LOLs.
This support is added through the already existing loop-doloop
mechanisms that are used for
urn true if an insn is an MVE instruction that VPT-predicable,
but in
+ its unpredicated form, or if it is predicated, but on a predicate
other
+ than vpr_reg. */
In this one also 'is a MVE instruction that is VPT-predicable' would
be better I think.
Oops, thanks for spotting.
gle_set (next_use_insn))
+ return true;
Assumes single_set doesn't return 0.
Thanks! That is indeed correct.
Corrected this by having a utility function to scan insn operands and
check against mve_memory_operand that supports any number of
operands/SETs in the insn
Let&#x
Hi all,
We've recently sent up a lot of patches overhauling the testsuite of the
Arm MVE backend.
With these changes, we've also identified and fixed a number of bugs
(some backend bugs and many to do with the polymorphism of intrinsics in
MVE the header file).
These would all be relevant to
On 17/05/2023 10:26, Kyrylo Tkachov wrote:
Hi Stam,
-Original Message-
From: Stam Markianos-Wright
Sent: Tuesday, May 16, 2023 2:32 PM
To: gcc-patches@gcc.gnu.org
Cc: Kyrylo Tkachov ; Richard Earnshaw
; Andrea Corallo
Subject: [GCC12 backport] arm: MVE testsuite and backend bugfixes
On 23/05/2023 15:41, Christophe Lyon wrote:
Glibc defines int32_t as 'int' while newlib defines it as 'long int'.
Although these correspond to the same size, g++ complains when using the
er is
used twice as "vmov q0[2], q0[0], r2, r2" and the reg
num might also not always be guaranteed).
No regressions on MVE tesctsuite configurations or in
the CMSIS-NN testsuite.
Ok for trunk? (Despite this being late in Stage 4, sorry
about that!)
Thanks,
Stamatis Markianos-Wright
needs backports as well, right?
Indeed! I'm building up a larger list of commits that we're hoping
to backport, so I will include this on that list.
Thanks,
Kyrill
Thanks,
Stamatis Markianos-Wright
gcc/ChangeLog:
* config/arm/mve.md (mve_vcvtq_n_to_f_): Swap
operands.
Hi all,
This is just a minor issue I found with a previous test
of mine that caused it to fail in C++ mode due to these
unused const variables being uninitialised. I forgot to
remove these after removing some test cases that did use
them.
I removed the test cases, because I came to the
conclusion
On 02/05/2023 09:28, Christophe Lyon wrote:
Hi Stam!
On 4/28/23 13:30, Andrea Corallo via Gcc-patches wrote:
From: Stam Markianos-Wright
Hi all,
This is a simple testsuite tidy-up patch, addressing to types of errors:
* The vcmp vector-scalar tests failing due to the compiler's preferenc
On 28/04/2023 17:54, Kyrylo Tkachov wrote:
-Original Message-
From: Andrea Corallo
Sent: Friday, April 28, 2023 12:30 PM
To: gcc-patches@gcc.gnu.org
Cc: Kyrylo Tkachov ; Richard Earnshaw
; Stam Markianos-Wright
Subject: [PATCH 09/10] arm testsuite: XFAIL or relax registers in some t
On 28/04/2023 17:45, Kyrylo Tkachov wrote:
Hi Andrea, Stam,
-Original Message-
From: Andrea Corallo
Sent: Friday, April 28, 2023 12:30 PM
To: gcc-patches@gcc.gnu.org
Cc: Kyrylo Tkachov ; Richard Earnshaw
; Stam Markianos-Wright
Subject: [PATCH 04/10] arm: Stop vadcq, vsbcq intrinsics
Hi Kyrill,
On 28/04/2023 17:58, Kyrylo Tkachov wrote:
-Original Message-
From: Andrea Corallo
Sent: Friday, April 28, 2023 12:30 PM
To: gcc-patches@gcc.gnu.org
Cc: Kyrylo Tkachov ; Richard Earnshaw
; Stam Markianos-Wright
Subject: [PATCH 10/10] arm testsuite: Shifts and get_FPSCR ACL
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