Sorry, didn't include changelog. Here is it:
gcc/
* common/config/i386/i386-common.c
(OPTION_MASK_ISA_SGX_UNSET, OPTION_MASK_ISA_SGX_SET): New.
(ix86_handle_option): Handle OPT_msgx.
* config.gcc: Added sgxintrin.h.
* config/i386/cpuid.h (bit_SGX): New.
* config/i386/
28, 2016 at 11:22 AM, Yulia Koval wrote:
>> Thank you,
>> Here is the repost.
>>
>> Update TARGET_FUNCTION_INCOMING_ARG documentation
>>
>> On x86, interrupt handlers are only called by processors which push
>> interrupt data onto stack at t
Thank you,
Here is the repost.
Update TARGET_FUNCTION_INCOMING_ARG documentation
On x86, interrupt handlers are only called by processors which push
interrupt data onto stack at the address where the normal return address
is. Since interrupt handlers must access interrupt data via po
Hi,
This patch fixes the issue, when target(arch="haswell") function was
chosen instead of target(arch="skylake") on skylake. Ok for trunk?
gcc/
* config/i386/i386.c: Handle "skylake" and
"skylake-avx512".
gcc/testsuite/
* g++.dg/ext/mv16.C: New functions.
Yulia
patch_skylake
De
Hi,
I updated and reposted the patch. Regtested/bootstraped on
x86_64/Linux and i686/Linux. Ok for trunk?
Implement x86 interrupt attribute
The interrupt and exception handlers are called by x86 processors. X86
hardware pushes information onto stack and calls the handler. The
requirements are
Here it is.
gcc/
* config/i386/i386.c (m_SKYLAKE_AVX512): Fix typo.
Yulia
On Tue, Nov 3, 2015 at 5:32 PM, Uros Bizjak wrote:
> On Tue, Nov 3, 2015 at 3:16 PM, Yulia Koval wrote:
>> Hi,
>>
>> This patch fixes a typo: PROCESSOT -> PROCESSOR. Ok for trunk?
>
Hi,
This patch fixes a typo: PROCESSOT -> PROCESSOR. Ok for trunk?
Yulia
patch
Description: Binary data
se.
* gcc.target/i386/interrupt-redzone-2.c: Likewise.
* gcc.target/i386/interrupt-sibcall.c: Likewise.
* gcc.target/i386/interrupt-switch-abi.c: Likewise.
* gcc.target/i386/interrupt-xmm.c: Likewise.
* gcc.target/i386/interrupt-ymm.c: Likewise.
* gcc.target/i386/interrupt-zmm.c
uct interrupt_frame*)frame)->cs
$3 = 0x111
(gdb) p/x ((struct interrupt_frame*)frame)->flags
$4 = 0x333
Frame pointer info looks ok.
On Tue, Oct 13, 2015 at 3:18 PM, Yulia Koval wrote:
>
> Here is the current version of the patch with all the fixes.
> Regtested\bootstraped it on 64
Hi,
This patch fixes the issue:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67963
gcc/config/i386/i386.c (ix86_option_override_internal) Disable
80387 mask if lakemont target is set.
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 4c25c9e..db722aa 100644
--- a/gcc/confi
Here is the current version of the patch with all the fixes.
Regtested\bootstraped it on 64 bit.
We need a pointer since interrupt handler will update data pointing
to by frame. Since error_code isn't at the normal location where the
parameter is passed on stack and frame isn't in a hard register
interrupt-sibcall.c: Likewise.
* gcc.target/i386/interrupt-switch-abi.c: Likewise.
* gcc.target/i386/interrupt-xmm.c: Likewise.
* gcc.target/i386/interrupt-ymm.c: Likewise.
* gcc.target/i386/interrupt-zmm.c: Likewise.
On Fri, Oct 2, 2015 at 8:48 PM, Yulia Koval wrote:
> Fixed it. Thanks.
>
&
Fixed it. Thanks.
On Fri, Oct 2, 2015 at 6:45 PM, Uros Bizjak wrote:
> On Fri, Oct 2, 2015 at 2:51 PM, Yulia Koval wrote:
>> Hi,
>> Here is a new patch. Added HJ's changes and review changes.
>>
>> Implement x86 interrupt attribute
>
> +
* gcc.target/i386/interrupt-ymm.c: Likewise.
* gcc.target/i386/interrupt-zmm.c: Likewise.
Julia
On Thu, Oct 1, 2015 at 7:18 PM, Uros Bizjak wrote:
> On Thu, Oct 1, 2015 at 6:08 PM, H.J. Lu wrote:
>> On Thu, Oct 1, 2015 at 8:59 AM, Uros Bizjak wrote:
>>> On Thu, Oct 1, 201
Hi,
The patch below contains some tuning changes for Lakemont, introduced
by H.J. Lu. Bootstraped/regtested for Linux/x86_64. Ok for trunk?
* gcc/config/i386/x86-tune.def (X86_TUNE_USE_BT): Enable
for Lakemont.
(X86_TUNE_ZERO_EXTEND_WITH_AND): Disable for Lakemont.
Julia
Likewise.
* gcc.target/i386/interrupt-xmm.c: Likewise.
* gcc.target/i386/interrupt-ymm.c: Likewise.
* gcc.target/i386/interrupt-zmm.c: Likewise.
Julia
On Thu, Oct 1, 2015 at 3:24 AM, H.J. Lu wrote:
> On Wed, Sep 30, 2015 at 12:53 PM, Yulia Ko
Done.
Julia
On Wed, Sep 30, 2015 at 9:59 PM, H.J. Lu wrote:
> On Wed, Sep 30, 2015 at 5:36 AM, Yulia Koval wrote:
>> Hi,
>>
>> Thanks. I added all fixes to the patch, bootstrapped/regtested it on
>> Linux/x86_64. Linux/i686 in progress. Ok for trunk if tes
Tests for Linux/i686 passed successfully.
Julia
On Wed, Sep 30, 2015 at 3:48 PM, H.J. Lu wrote:
> On Wed, Sep 30, 2015 at 5:36 AM, Yulia Koval wrote:
>> Hi,
>>
>> Thanks. I added all fixes to the patch, bootstrapped/regtested it on
>> Linux/x86_64. Linux/i686 i
Hi,
Thanks. I added all fixes to the patch, bootstrapped/regtested it on
Linux/x86_64. Linux/i686 in progress. Ok for trunk if testing passes
successfully?
Julia
On Wed, Sep 30, 2015 at 5:50 AM, H.J. Lu wrote:
> On Tue, Sep 29, 2015 at 5:02 PM, H.J. Lu wrote:
>> On Tue, Sep 29, 2015 at 4:53 PM
Hi,
The patch below implements interrupt attribute for x86 processors.
The interrupt and exception handlers are called by x86 processors.
X86 hardware pushes information onto stack and calls the handler. The
requirements are
1. Both interrupt and exception handlers must use the 'IRET'
ins
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