[PATCH 2/2] Uninitialized padding in struct _dep.

From: Andrew Pinski In struct _dep, there is an implicit padding of 4bits. This bit-field padding is uninitialized when init_dep_1 is being called. This means we access uninitialized memory but never use it for anything. Adding an unused bit-field field and initializing it in init_dep_1 will im

[PATCH 1/2] Fix uninitialized field in expand_operand.

From: Andrew Pinski Commit g:f96bf49a0 added the target field to expand_operand. But it leaves it uninitialized when doing a full initialization inside create_expand_operand. This fixes the problem and improves the code generation inside create_expand_operand too. OK? Bootstrapped and tested on

[PATCH] Decrease cortexa57_extra_costs's alu.shift_reg

From: Andrew Pinski Like I mentioned in https://gcc.gnu.org/ml/gcc/2020-01/msg00157.html, The shift by a register should be just COSTS_N_INSNS (1) rather than COSTS_N_INSNS (2). This allows lshift_cheap_p to return true now and converting switches to be using shift and other like structures. I

[PATCHv2] Add initial octeontx2 support.

From: Andrew Pinski This adds octeontx2 naming. It currently uses the cortexa57 cost model and schedule model until I submit this. This is more a place holder to get the naming of the cores in GCC 10. I will submit the cost model in the next couple of days. OK? Bootstrapped and tested on aarc

[PATCH] Add initial octeontx2 support.

From: Andrew Pinski This adds octeontx2 naming. It currently uses the cortexa57 cost model and schedule model until I submit this. This is more a place holder to get the naming of the cores in GCC 10. I will submit the cost model in the next couple of days. OK? Bootstrapped and tested on aarc

[PATCH] Fix libstdc++ compiling for an aarch64 multilib with big-endian.

From: Andrew Pinski Hi if we have a aarch64 compiler that has a big-endian multi-lib, it fails to compile libstdc++ because simd_fast_mersenne_twister_engine is only defined for little-endian in ext/random but ext/opt_random.h thinks it is defined always. OK? Built an aarch64-elf toolchain whic

[PATCH] Fix PR 81721: ICE with PCH and Pragma warning and C++ operator

From: Andrew Pinski Hi, The problem here is the token->val.node is not saved over a precompiled header for C++ operator. This can cause an internal compiler error as we tried to print out the spelling of the token as we assumed it was valid. The fix is to have cpp_token_val_index return CPP_TO

[PATCH] [AARCH64] Improve vector generation cost model

From: Andrew Pinski Hi, On OcteonTX2, ld1r and ld1 (with a single lane) are split into two different micro-ops unlike most other targets. This adds three extra costs to the cost table: ld1_dup: used for "ld1r {v0.4s}, [x0]" merge_dup: used for "dup v0.4s, v0.4s[0]" and "ins v0.4s[0], v0.4s[0]"

[PATCH] [PATCH/AARCH64] Use neon_move instead of move_logic in some places

From: Andrew Pinski Hi, In some places in the aarch64 backend, neon_logic is used for mov v0.16b, v1.16b mov v0., v1. This patch moves them over to use neon_move instead. For most cores, this does not matter but for OcteonTX2 core it does matter. OK? Bootstrapped and tested on aarch64-linux-g

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