[PATCH] RISC-V: Fix FIXED_REGISTERS comment missing return address register

From: Yixuan Chen gcc/config/ChangeLog: 2024-09-24 Yixuan Chen * riscv/riscv.h: Fix FIXED_REGISTERS comment missing return address register. --- gcc/config/riscv/riscv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/

[PATCH] minimal support for xtheadv

From: XYenChi This patch is for support xtheadv. gcc/ChangeLog: 2023-11-08 Chen Yixuan * common/config/riscv/riscv-common.cc: Add xthead minimal support. gcc/config/ChangeLog: 2023-11-08 Chen Yixuan * riscv/riscv.opt: Add xthead minimal support. --- gcc/common/config/

[PATCH] Add VXRM enum

From: XYenChi Noticed that the rvv-intrinsic-doc updated the __RISCV_VXRM. gcc/ChangeLog:Add __RISCV_VXRM enum to riscv_vector.h 2023-07-13 XYenChi * config/riscv/riscv_vector.h (enum __RISCV_VXRM):Add an enum __RISCV_VXRM to help express the rounding modes. --- gcc/config/riscv/

[PATCH] Changed vector size

From: Yixuan Chen Observed a vint type "ABS_EXPR" followed by extra 3 int type "ABS_EXPR". If want to test absolute value optimization for vector, maybe don't need 4 times. gcc/testsuite/ChangeLog: 2023-03-27 Yixuan Chen * g++.dg/pr94920.C: Declare the vector size as long as int.