Hi,
The below patch fixes the FFT/Scimark regression caused by useless prefetch
generation.
This fix tries to make prefetch less aggressive by prefetching arrays in the
inner loop, when the step is invariant in the entire loop nest.
GCC currently tries to prefetch invariant steps when they are
Hi Maintainers,
This patch enables "prefetchw" ISA in the processor alias table for targets
amdfam10,barcelona and bdver1,2 and btver1,2.
GCC regression test passes with the patch.
Ok for trunk?
Change log:
2012-09-11 Venkataramanan Kumar
* config/i386/i386.c (processor_alias_table):
Hi Maintainers,
Below patch does the basic enablement for next generation AMD low power btver2
core.
It defines -march=btver2 and -mtune=btver2, and lets -march=native correctly
recognizes btver2. At the moment the tuning is mostly a copy of btver1.
The patch passed bootstrap and the x86 tests.
Hi Maintainers,
Please find the patch below that backports PR target/52908 to GCC 4.7.
The patch passed bootstrap and regression test.
Ok to commit?
regards,
Venkat.
Index: ChangeLog
===
--- ChangeLog (revision 187449)
+++ Chan
> Subject: Re: [Gcc.amd] [Patch 001] [x86 backend] Define march/mtune for
> upcoming AMD Bulldozer procesor.
>
> > Hello!
> >
> > > This patch defines -march=bdver1 and -mtune=bdver1 flag for the upcoming
> > > AMD Bulldozer processor.
> Hi,
> it seems that bdver/btver is not mentioned in invoke.t
> Subject: Re: [Gcc.amd] [Patch 001] [x86 backend] Define march/mtune for
> upcoming AMD Bulldozer procesor.
>
> > Hello!
> >
> > > This patch defines -march=bdver1 and -mtune=bdver1 flag for the upcoming
> > > AMD Bulldozer processor.
> Hi,
> it seems that bdver/btver is not mentioned in invoke.t
