Hi,
I spotted in an assembly dump, that the the SHLL, SHLL2, SADDL, and SSUBL
instructions appear out of line, as they are missing a tab between their
mnemonic and their operands.
I've committed (revision 217917) the attached as the obvious fix to this.
Tested with a build-test and a run of aarch64.exp/simd.exp for
aarch64-none-elf with no issues.
Cheers,
James
---
2014-11-21 James Greenhalgh <james.greenha...@arm.com>
* config/aarch64/aarch64-simd.md
(aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>): Add a tab between
output mnemonic and operands.
(aarch64_simd_vec_unpack<su>_lo_<mode>): Likewise.
(aarch64_simd_vec_unpack<su>_hi_<mode>): Likewise.
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 23345b1df1ebb28075edd2effd5f327749abd61d..926eb765e1bdc84f3f7873dbcd4030c4e2ea62a7 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1175,7 +1175,7 @@ (define_insn "aarch64_simd_vec_unpack<su
(match_operand:VQW 2 "vect_par_cnst_lo_half" "")
)))]
"TARGET_SIMD"
- "<su>shll %0.<Vwtype>, %1.<Vhalftype>, 0"
+ "<su>shll\t%0.<Vwtype>, %1.<Vhalftype>, 0"
[(set_attr "type" "neon_shift_imm_long")]
)
@@ -1186,7 +1186,7 @@ (define_insn "aarch64_simd_vec_unpack<su
(match_operand:VQW 2 "vect_par_cnst_hi_half" "")
)))]
"TARGET_SIMD"
- "<su>shll2 %0.<Vwtype>, %1.<Vtype>, 0"
+ "<su>shll2\t%0.<Vwtype>, %1.<Vtype>, 0"
[(set_attr "type" "neon_shift_imm_long")]
)
@@ -2601,7 +2601,7 @@ (define_insn "aarch64_<ANY_EXTEND:su><AD
(ANY_EXTEND:<VWIDE>
(match_operand:VDW 2 "register_operand" "w"))))]
"TARGET_SIMD"
- "<ANY_EXTEND:su><ADDSUB:optab>l %0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
+ "<ANY_EXTEND:su><ADDSUB:optab>l\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "type" "neon_<ADDSUB:optab>_long")]
)
