Bootstrapped and regression tested on s390x. Committed to mainline.
gcc/ChangeLog: * config/s390/s390.md (*not<mode>): New pattern. gcc/testsuite/ChangeLog: * gcc.target/s390/not.c: New test. --- gcc/config/s390/s390.md | 8 ++++++++ gcc/testsuite/gcc.target/s390/not.c | 11 +++++++++++ 2 files changed, 19 insertions(+) create mode 100644 gcc/testsuite/gcc.target/s390/not.c diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 0e56fbad44d..4828aa08be6 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -8302,6 +8302,14 @@ "n<ANDOR:inv_no><GPR:g>rk\t%0,%1,%2" [(set_attr "op_type" "RRF")]) +; Use NAND for bit inversion +(define_insn "*not<mode>" + [(set (match_operand:GPR 0 "register_operand" "=d") + (not:GPR (match_operand:GPR 1 "register_operand" "d"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_Z15" + "nn<GPR:g>rk\t%0,%1,%1" + [(set_attr "op_type" "RRF")]) ; ; Block inclusive or (OC) patterns. diff --git a/gcc/testsuite/gcc.target/s390/not.c b/gcc/testsuite/gcc.target/s390/not.c new file mode 100644 index 00000000000..dae95f7d8a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/not.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z15 -mzarch" } */ + +unsigned long +foo (unsigned long a) +{ + return ~a; +} + +/* { dg-final { scan-assembler-times "\tnngrk\t" 1 { target { lp64 } } } } */ +/* { dg-final { scan-assembler-times "\tnnrk\t" 1 { target { ! lp64 } } } } */ -- 2.39.0