On Thu, Jul 9, 2015 at 10:17 PM, Jakub Jelinek <ja...@redhat.com> wrote: > On Thu, Jul 09, 2015 at 10:13:49PM +0200, Uros Bizjak wrote: >> I was under impression that peephole2 pass doesn't see subregs of hard >> regs (all x86 predicates are written in this way). Even documentation >> somehow agrees with this:
[...] >> So, I'd say that generating naked SUBREG after reload should be >> avoided and gen_lowpart should be used in the code above. > > There is also: > emit_insn (gen_sse2_loadld (operands[3], CONST0_RTX (V4SImode), > gen_rtx_SUBREG (SImode, operands[1], 0))); > emit_insn (gen_sse2_loadld (operands[4], CONST0_RTX (V4SImode), > gen_rtx_SUBREG (SImode, operands[1], 4))); > in some splitters (also post-reload). Attached patch converts all relevant places to gen_lowpart/gen_highpart to prevent subregs of a hard register after reload. 2015-07-10 Uros Bizjak <ubiz...@gmail.com> * config/i386/sse.md (movdi_to_sse): Use gen_lowpart and gen_higpart instead of gen_rtx_SUBREG. * config/i386/i386.md (floatdi<X87MODEF:mode>2_i387_with_xmm splitter): Ditto. (read-modify peephole2): Use gen_lowpart instead of gen_rtx_SUBREG for operand 5. Patch was bootstrapped (with --enable-checking=rtl) and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline, will be backported to gcc-5 branch together with PR 66814 patch once branch opens. Uros.
Index: config/i386/i386.md =================================================================== --- config/i386/i386.md (revision 225675) +++ config/i386/i386.md (working copy) @@ -5100,11 +5100,11 @@ /* The DImode arrived in a pair of integral registers (e.g. %edx:%eax). Assemble the 64-bit DImode value in an xmm register. */ emit_insn (gen_sse2_loadld (operands[3], CONST0_RTX (V4SImode), - gen_rtx_SUBREG (SImode, operands[1], 0))); + gen_lowpart (SImode, operands[1]))); emit_insn (gen_sse2_loadld (operands[4], CONST0_RTX (V4SImode), - gen_rtx_SUBREG (SImode, operands[1], 4))); + gen_highpart (SImode, operands[1]))); emit_insn (gen_vec_interleave_lowv4si (operands[3], operands[3], - operands[4])); + operands[4])); operands[3] = gen_rtx_REG (DImode, REGNO (operands[3])); }) @@ -18064,11 +18064,13 @@ operands[1] = gen_rtx_PLUS (word_mode, base, gen_rtx_MULT (word_mode, index, GEN_INT (scale))); - operands[5] = base; if (mode != word_mode) operands[1] = gen_rtx_SUBREG (mode, operands[1], 0); + + operands[5] = base; if (op1mode != word_mode) - operands[5] = gen_rtx_SUBREG (op1mode, operands[5], 0); + operands[5] = gen_lowpart (op1mode, operands[5]); + operands[0] = dest; }) Index: config/i386/sse.md =================================================================== --- config/i386/sse.md (revision 225675) +++ config/i386/sse.md (working copy) @@ -1080,9 +1080,9 @@ /* The DImode arrived in a pair of integral registers (e.g. %edx:%eax). Assemble the 64-bit DImode value in an xmm register. */ emit_insn (gen_sse2_loadld (operands[0], CONST0_RTX (V4SImode), - gen_rtx_SUBREG (SImode, operands[1], 0))); + gen_lowpart (SImode, operands[1]))); emit_insn (gen_sse2_loadld (operands[2], CONST0_RTX (V4SImode), - gen_rtx_SUBREG (SImode, operands[1], 4))); + gen_highpart (SImode, operands[1]))); emit_insn (gen_vec_interleave_lowv4si (operands[0], operands[0], operands[2])); }