Hi,
GCC uses full 512-bit register in case of moving SF/DF value between two
registers.
The patch avoid 512-bit register usage if "-mprefer-avx256" option used.
2017-10-06 Sergey Shalnov
gcc/
* config/i386/i386.md(*movsf_internal, *movdf_internal):
Avoid 512-bit AVX modes for
7;gcc-patches@gcc.gnu.org' ; 'ubiz...@gmail.com'
; 'kirill.yuk...@gmail.com' ;
Senkevich, Andrew ; Ivchenko, Alexander
; Peryt, Sebastian
Subject: Re: [PATCH, i386] Avoid 512-bit mode MOV for prefer-avx256 option in
Intel AVX512 configuration
On Fri, Oct 06, 2017 at 09:
iz...@gmail.com'
; 'kirill.yuk...@gmail.com' ;
Senkevich, Andrew ; Ivchenko, Alexander
; Peryt, Sebastian
Subject: RE: [PATCH, i386] Avoid 512-bit mode MOV for prefer-avx256 option in
Intel AVX512 configuration
Jakub,
I completely agree with you. I fixed the patch.
Currently, TARGET_PREFER
Hello Sergey,
On 06 Oct 14:20, Shalnov, Sergey wrote:
> Jakub,
> I completely agree with you. I fixed the patch.
> Currently, TARGET_PREFER256 will work on architectures with 512VL. It will
> not work otherwise.
>
> I will try to find better solution for this. I think I need to look into
> regis
alnov, Sergey
Cc: Jakub Jelinek ; 'gcc-patches@gcc.gnu.org'
; 'ubiz...@gmail.com' ; Senkevich,
Andrew ; Ivchenko, Alexander
; Peryt, Sebastian
Subject: Re: [PATCH, i386] Avoid 512-bit mode MOV for prefer-avx256 option in
Intel AVX512 configuration
Hello Sergey,
On 06 Oct 14:
; Ivchenko, Alexander
> ; Peryt, Sebastian
> Subject: Re: [PATCH, i386] Avoid 512-bit mode MOV for prefer-avx256 option in
> Intel AVX512 configuration
>
> Hello Sergey,
> On 06 Oct 14:20, Shalnov, Sergey wrote:
> > Jakub,
> > I completely agree with you. I fixed th
On Fri, Oct 06, 2017 at 09:33:21AM +, Shalnov, Sergey wrote:
> Hi,
> GCC uses full 512-bit register in case of moving SF/DF value between two
> registers.
> The patch avoid 512-bit register usage if "-mprefer-avx256" option used.
>
> 2017-10-06 Sergey Shalnov
>
> gcc/
> * config/i38
