On Mon, Feb 27, 2023 at 04:03:56PM -0600, Pat Haugen wrote:
> On 2/27/23 2:53 PM, Segher Boessenkool wrote:
> >"Slightly". It takes 12 cycles for the two in parallel (64-bit, p9),
> >but 17 cycles for the "cheaper" sequence (divd+mulld+subf, 12+5+2). It
> >is all worse if the units are busy of co
On 2/27/23 2:53 PM, Segher Boessenkool wrote:
Hi!
On Mon, Feb 27, 2023 at 02:12:23PM -0600, Pat Haugen wrote:
On 2/27/23 11:08 AM, Segher Boessenkool wrote:
On Mon, Feb 27, 2023 at 09:11:37AM -0600, Pat Haugen wrote:
The define_insns for the modulo operation currently force the target
registe
Hi!
On Mon, Feb 27, 2023 at 02:12:23PM -0600, Pat Haugen wrote:
> On 2/27/23 11:08 AM, Segher Boessenkool wrote:
> >On Mon, Feb 27, 2023 at 09:11:37AM -0600, Pat Haugen wrote:
> >>The define_insns for the modulo operation currently force the target
> >>register
> >>to a distinct reg in preparation
On 2/27/23 11:08 AM, Segher Boessenkool wrote:
Hi!
On Mon, Feb 27, 2023 at 09:11:37AM -0600, Pat Haugen wrote:
The define_insns for the modulo operation currently force the target
register
to a distinct reg in preparation for a possible future peephole combining
div/mod. But this can lead to ca
Hi!
On Mon, Feb 27, 2023 at 09:11:37AM -0600, Pat Haugen wrote:
> The define_insns for the modulo operation currently force the target
> register
> to a distinct reg in preparation for a possible future peephole combining
> div/mod. But this can lead to cases of a needless copy being inserted. Fi
Don't force target of modulo into a distinct register.
The define_insns for the modulo operation currently force the target
register
to a distinct reg in preparation for a possible future peephole combining
div/mod. But this can lead to cases of a needless copy being inserted. Fixed
with the fo
