[PATCH] Fix mismatch between constraint and predicate for ashl3_doubleword.

efine_insn "ashl3_doubleword" [(set (match_operand:DWI 0 "register_operand" "=,") (ashift:DWI (match_operand:DWI 1 "reg_or_pm1_operand" "0n,r") (match_operand:QI 2 "nonmemory_operand" "c,c"))) The patch

[PATCH] MIPS: Add some floating point instructions support for MIPSr6

This patch adds some floating point instructiions from mips32r6, for instance, MINA/MAXA.fmt, RINT.fmt, CLASS.fmt etc. Also add built-in functions to MIPSr6 to better handle tests for MIPSr6. gcc/ChangeLog: * config/mips/i6400.md (i6400_fpu_minmax): Include fclass type

Re: [PATCH 2/3] isel: Small cleanup of duplicating comparisons

On Fri, Jul 26, 2024 at 6:37 AM Andrew Pinski wrote: > > This is a small cleanup of the duplicating comparison code. > There is code generation difference but only for -O0 and -fno-tree-ter > (both of which will be fixed in a later patch). > The difference is instead of skippin

Re: [PATCH 1/3] isel: Move duplicate comparisons to its own function

On Fri, Jul 26, 2024 at 6:37 AM Andrew Pinski wrote: > > This is just a small cleanup to isel and no functional changes just. > The loop inside pass_gimple_isel::execute looked was getting too > deap so let's fix that by moving it to its own function. > > Bootstrapped and tested on

Re: [PATCH 3/3] isel: Don't duplicate comparisons for -O0 nor -fno-tree-ter [PR116101]

On Fri, Jul 26, 2024 at 6:37 AM Andrew Pinski wrote: > > While doing cleanups on this code I noticed that we do the duplicate > of comparisons at -O0. For C and C++ code this makes no difference as > the gimplifier never produces COND_EXPR. But it could make a difference > for other front-ends. >

Re: [PATCH] MATCH: Optimize `VEC_SHL_INSERT (dup (A), A)` to just `dup (A) [PR116075]

s to see if this is optimized since the > > > auto-vectorizer or intrinsics are the only two ways of getting this > > > produced. > > > > > > Build and tested for aarch64-linux-gnu with no regressions. > > > > For the case in question implementing fold_const_cal

Re: [PATCH Ping] i386: Use BLKmode for {ld,st}tilecfg

On Fri, Jul 26, 2024 at 2:28 PM Jiang, Haochen wrote: > > Ping for this patch > > Thx, > Haochen > > > -Original Message- > > From: Haochen Jiang > > Sent: Thursday, July 18, 2024 9:45 AM > > To: gcc-patches@gcc.gnu.org > > Cc: Liu, Hong

RE: [PATCH] i386: Fix AVX512 intrin macro typo

> -Original Message- > From: Jakub Jelinek > Sent: Friday, July 26, 2024 2:31 PM > To: Jiang, Haochen > Cc: gcc-patches@gcc.gnu.org; Liu, Hongtao ; > ubiz...@gmail.com > Subject: Re: [PATCH] i386: Fix AVX512 intrin macro typo > > On Fri, Jul 26, 2024 at 02:2

[PATCH] i386: Add non-optimize prefetchi intrins

Hi all, Under -O0, with the "newly" introduced intrins, the variable will be transformed as mem instead of the origin symbol_ref. The compiler will then treat the operand as invalid and turn the operation into nop, which is not expected. Use macro for non-optimize to keep the variable as

Re: [PATCH] i386: Fix AVX512 intrin macro typo

On Fri, Jul 26, 2024 at 02:25:22PM +0800, Haochen Jiang wrote: > Hi all, > > There are several typo in AVX512 intrins macro define. They will eventually > result in errors with -O0. This patch will fix that. Add a testcase that verifies that? > Bootstrapped on x86-64-pc-linux-gn

Re: [PATCH] aarch64: Fix target/optimize option handling with transiting between O1 to O2

On Thu, Jul 25, 2024 at 10:25 PM Andrew Pinski wrote: > > The problem here is the aarch64 backend enables -mearly-ra at -O2 and above > but > it is not marked as an Optimization in the .opt file so enabling it sometimes > reset the target options when going from -O1 to -O2 for the first time. >

RE: [PATCH Ping] i386: Use BLKmode for {ld,st}tilecfg

Ping for this patch Thx, Haochen > -Original Message- > From: Haochen Jiang > Sent: Thursday, July 18, 2024 9:45 AM > To: gcc-patches@gcc.gnu.org > Cc: Liu, Hongtao ; hjl.to...@gmail.com; > ubiz...@gmail.com > Subject: [PATCH] i386: Use BLKmode for {ld,s

[PATCH] i386: Fix AVX512 intrin macro typo

Hi all, There are several typo in AVX512 intrins macro define. They will eventually result in errors with -O0. This patch will fix that. Bootstrapped on x86-64-pc-linux-gnu. Ok for trunk and backport to GCC14, GCC 13 and GCC 12? Thx, Haochen gcc/ChangeLog: * config/i386

[PATCH]AArch64: check for vector mode in get_mask_mode [PR116074]

Hi All, For historical reasons AArch64 has TI mode vector types but does not consider TImode a vector mode. What's happening in the PR is that get_vectype_for_scalar_type is returning vector(1) TImode for a TImode scalar. This then fails when we call targetm.vectorize.get_mask_mode

Re: [PATCH] c++/modules: Stream warning suppressions [PR115757]

> > > -- >8 -- > > > > > > Currently we don't stream the contents of 'nowarn_map'; this means that > > > warning suppressions don't get applied in importers, which is > > > particularly relevant for templates (as in the linked testcase). > > >

Re: [PATCH] c++/modules: Ensure deduction guides are always reachable [PR115231]

ormal' functions currently, and > > have no special handling in modules. However, this causes some issues; > > by [temp.deduct.guide] a deduction guide is not found by normal name > > lookup and instead all reachable deduction guides for a class template > > should be cons

[PATCH 2/3] isel: Small cleanup of duplicating comparisons

This is a small cleanup of the duplicating comparison code. There is code generation difference but only for -O0 and -fno-tree-ter (both of which will be fixed in a later patch). The difference is instead of skipping the first use if the comparison uses are only in cond_expr we skip the last use

[PATCH 1/3] isel: Move duplicate comparisons to its own function

This is just a small cleanup to isel and no functional changes just. The loop inside pass_gimple_isel::execute looked was getting too deap so let's fix that by moving it to its own function. Bootstrapped and tested on x86_64-linux-gnu with no regressions. gcc/ChangeLog: * gimple-isel.cc

[PATCH 3/3] isel: Don't duplicate comparisons for -O0 nor -fno-tree-ter [PR116101]

While doing cleanups on this code I noticed that we do the duplicate of comparisons at -O0. For C and C++ code this makes no difference as the gimplifier never produces COND_EXPR. But it could make a difference for other front-ends. Oh and for -fno-tree-ter, duplicating the comparison is just a

Re: [PATCH] rs6000, Add new overloaded vector shift builtin int128, varients

Peter, Segher: On 7/23/24 2:26 PM, Peter Bergner wrote: On 7/19/24 3:04 PM, Carl Love wrote: diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 5af9bf920a2..2a18ee44526 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -878,9 +878,9 @@

Re: [PATCH] rs6000, Add new overloaded vector shift builtin int128, varients

Kewen: On 7/25/24 1:21 AM, Kewen.Lin wrote: Hi Carl, Some minor comments are inlined on top of Segher's and Peter's comments. on 2024/7/20 04:04, Carl Love wrote: GCC developers: The following patch adds the int128 varients to the existing overloaded built-ins vec_sld, vec_sldb, vec_sldw

[PATCH] gimple-ssa-sprintf: Fix typo in range check

The code to scale ranges for wide chars in format_string incorrectly checks range.likely to scale range.unlikely, which is a copy-paste typo from the immediate previous condition. gcc/ChangeLog: gimple-ssa-sprintf.cc (format_string): Fix type in range check for UNLIKELY for wide

Re: [PATCH v1 1/2] PR116080: Fix tail call dejagnu checks

On Thu, Jul 25, 2024 at 4:09 PM Sam James wrote: > > Andi Kleen writes: > > > From: Andi Kleen > > > > - Run the target_effective tail_call checks without optimization to > > match the actual test cases. > > - Add an extra check for external tail calls to handle targets like > > powerpc that

Re: [PATCH v1 1/2] PR116080: Fix tail call dejagnu checks

Andi Kleen writes: > From: Andi Kleen > > - Run the target_effective tail_call checks without optimization to > match the actual test cases. > - Add an extra check for external tail calls to handle targets like > powerpc that cannot tail call between different object files. > This one will also

[PATCH v1 2/2] PR116019: Improve tail call error message

From: Andi Kleen The "tail call must be the same type" message is common on some targets with C++, or without optimization. It is generated when gcc believes there is an access of the return value after the call. However usually it does not actually corespond to a type mismatch, but can be

[PATCH v1 1/2] PR116080: Fix tail call dejagnu checks

From: Andi Kleen - Run the target_effective tail_call checks without optimization to match the actual test cases. - Add an extra check for external tail calls to handle targets like powerpc that cannot tail call between different object files. This one will also cover templates.

Re: [PATCH 4/5] MATCH: Create BIT_ANDN and BIT_IORN from matching

On Thu, Jul 25, 2024 at 5:16 AM Richard Biener wrote: > > On Thu, Jul 25, 2024 at 4:16 AM Andrew Pinski > wrote: > > > > To better create rtl directly from gimple, we can use > > these already internal functions from the gimple. > > > > That is simplify `a & ~b` into BIT_ANDN. > > Likewise `a |

Re: [PATCH 2/2] rs6000, remove built-ins __builtin_vsx_set_1ti, __builtin_vsx_set_2df, __builtin_vsx_set_2di

Kewen: On 7/25/24 1:24 AM, Kewen.Lin wrote: optimization the number of assembly generated for the two methods are similar.  With -O3 optimization, the assembly generated for the two approaches is identical for the 2DF and 2DI types.  The assembly for the C-code version of the 1Ti requres one

Re: [PATCH 0/2] rs6000, remove vec and vsx set builtins

Kewen: On 7/25/24 1:21 AM, Kewen.Lin wrote: The patch, first patch in this series, to remove the __builtin_vec_set_v1ti, __builtin_vec_set_v2df, __builtin_vec_set_v2di was previously posted.  The feedback on the patch was that we could also remove set bif attribute.  Removal of the set bif

Re: [PATCH] MATCH: Optimize `VEC_SHL_INSERT (dup (A), A)` to just `dup (A) [PR116075]

> Build and tested for aarch64-linux-gnu with no regressions. > > For the case in question implementing fold_const_call would be better. Also … Makes sense, I have a patch which I am testing that does this. > > >PR target/116075 > > > > gcc/ChangeLog: > > > &

Re: [PATCH] c++: alias of alias tmpl with dependent attrs [PR115897]

ord "dependent" to the name of the new function. Done. So opaque_alias_p checks for type identity of an alias, whereas dependent_alias_template_spec_p more broadly checks for SFINAE identity. Something like the following (as an incremental patch on top of the previous one, to consid

[PATCH] aarch64: Fix target/optimize option handling with transiting between O1 to O2

The problem here is the aarch64 backend enables -mearly-ra at -O2 and above but it is not marked as an Optimization in the .opt file so enabling it sometimes reset the target options when going from -O1 to -O2 for the first time. Build and tested for aarch64-linux-gnu with no regressions.

Re: [PATCH 1/2] rs6000, Remove __builtin_vec_set_v1ti,, __builtin_vec_set_v2df, __builtin_vec_set_v2di

Kewen: On 7/25/24 1:22 AM, Kewen.Lin wrote: on 2024/7/24 01:52, Carl Love wrote: GCC maintainers: This patch was previously posted.  Per the feedback, it is now the first of two patches to remove the set built-ins. This patch removes the __builtin_vec_set_v1ti, __builtin_vec_set_v2df

Re: [PATCH 1/2] rs6000, Remove __builtin_vec_set_v1ti,, __builtin_vec_set_v2df, __builtin_vec_set_v2di

Kewen: On 7/25/24 1:22 AM, Kewen.Lin wrote: - rs6000, Remove __builtin_vec_set_v1ti, __builtin_vec_set_v2df, __builtin_vec_set_v2di Remove the built-ins, use the default gimple

Re: [PATCH v2] MATCH: Simplify (a ? x : y) eq/ne (b ? x : y) [PR111150]

On Thu, Jul 25, 2024 at 12:01 PM Adhemerval Zanella Netto wrote: > > > > On 17/07/24 14:00, Andrew Pinski wrote: > > On Wed, Jul 17, 2024 at 5:24 AM Richard Biener > > wrote: > >> > >> On Tue, Jul 16, 2024 at 3:36 PM Eikansh Gupta > >&g

Re: [PATCH v3 01/12] OpenMP: metadirective tree data structures and front-end interfaces

On 7/25/24 08:00, Tobias Burnus wrote: Hi Sandra, thanks for your patch. (Disclaimer: I have not finished reading through your patch.) Some upfront generic remarks: [* When first compiling it (incremental build), I did run into the issue that OMP_METADIRECTIVE_CHECK wasn't declared. Thus

Re: [PATCH v2] MATCH: Simplify (a ? x : y) eq/ne (b ? x : y) [PR111150]

On 17/07/24 14:00, Andrew Pinski wrote: > On Wed, Jul 17, 2024 at 5:24 AM Richard Biener > wrote: >> >> On Tue, Jul 16, 2024 at 3:36 PM Eikansh Gupta >> wrote: >>> >>> This patch adds match pattern for `(a ? x : y) eq/ne (b ? x : y)`. &g

Re: [PATCH] c++: alias of alias tmpl with dependent attrs [PR115897]

te_spec_p (and > > > > changing > > > > its name)? It seems like other callers would also benefit from that > > > > change. > > > > > > I ended up adding a new predicate opaque_alias_p separate from > > > dependent_alias_template_spec_p since ISTM we need to call it

Re: [PATCH] c++: structured bindings and lookup of tuple_size/tuple_element [PR115605]

On 6/25/24 1:00 AM, Andrew Pinski wrote: The problem here is even though we pass std namespace to lookup_template_class as the context, it will look at the current scope for the name too. The fix is to lookup the qualified name first and then use that for lookup_template_class. If

Re: [PATCH] c++: Implement C++26 P2558R2 - Add @, $, and ` to the basic character set [PR110343]

On 7/17/24 6:04 PM, Jakub Jelinek wrote: Hi! The following patch implements the easy parts of the paper. When @$` are added to the basic character set, it means that R"@$`()@$`" should now be valid (here I've noticed most of the raw string tests were tested solely with -std=c++11 o

Re: [PATCH] c++: alias of alias tmpl with dependent attrs [PR115897]

name)? It seems like other callers would also benefit from that > > > change. > > > > I ended up adding a new predicate opaque_alias_p separate from > > dependent_alias_template_spec_p since ISTM we need to call it from > > there and from alias_template_special

Re: [PATCH] MATCH: Optimize `VEC_SHL_INSERT (dup (A), A)` to just `dup (A) [PR116075]

> Am 25.07.2024 um 17:56 schrieb Andrew Pinski : > > It was noticed if we have `.VEC_SHL_INSERT ({ 0, ... }, 0)` it was not being > simplified to just `{ 0, ... }`. This was generated from the autovectorizer > (maybe even on accident, see PR tree-optmization/116081). > > This adds a few SVE

[PATCH] MATCH: Optimize `VEC_SHL_INSERT (dup (A), A)` to just `dup (A) [PR116075]

It was noticed if we have `.VEC_SHL_INSERT ({ 0, ... }, 0)` it was not being simplified to just `{ 0, ... }`. This was generated from the autovectorizer (maybe even on accident, see PR tree-optmization/116081). This adds a few SVE testcases to see if this is optimized since the auto-vectorizer or

Re: [PATCH v2] RISC-V: xtheadmemidx: Fix mode test for pre/post-modify addressing

g that out). This popped up when I was about to push, so I did not push yet. The last thing I want to do is interfere with the release process, so apologies for pushing the backport for PR116035 yesterday. I will wait with this patch for the GCC 14.2 release, rebase/retest and push then, unless

Re: [PATCH v2] RISC-V: xtheadmemidx: Fix mode test for pre/post-modify addressing

ped up when I was about to push, so I did not push yet. The last thing I want to do is interfere with the release process, so apologies for pushing the backport for PR116035 yesterday. I will wait with this patch for the GCC 14.2 release, rebase/retest and push then, unless the release manager or maintainers propose another procedure.

Re: [PATCH v2] RISC-V: xtheadmemidx: Fix mode test for pre/post-modify addressing

On Thu, 25 Jul 2024 08:10:25 PDT (-0700), jeffreya...@gmail.com wrote: On 7/25/24 9:06 AM, Christoph Müllner wrote: Ok, also to backport to GCC 14? Yes, of course. I'm OK with that, but according to the latest status report ,

Re: [PATCH v2] RISC-V: xtheadmemidx: Fix mode test for pre/post-modify addressing

On 7/25/24 9:06 AM, Christoph Müllner wrote: Ok, also to backport to GCC 14? Yes, of course. jeff

Re: [PATCH v2] RISC-V: xtheadmemidx: Fix mode test for pre/post-modify addressing

Ok, also to backport to GCC 14? On Thu, Jul 25, 2024 at 4:56 PM Jeff Law wrote: > > > > On 7/24/24 9:15 AM, Christoph Müllner wrote: > > auto_inc_dec (-O3) performs optimizations like the following > > if RVV and XTheadMemIdx is enabled. > > > > (insn 23 20 27 3 (set (mem:V4QI (reg:DI 136 [

Re: [patch,avr] Implement PR116056: attribute signal(n) and interrupt(n)

On 7/23/24 2:19 PM, Georg-Johann Lay wrote: This patch adds support for arguments to the signal and interrupt function attributes.  It allows to specify the ISR by means of the associated IRQ number, in extension to the current attributes that require to specify the ISR name like "__vec

Re: [PATCH v2] RISC-V: xtheadmemidx: Fix mode test for pre/post-modify addressing

On 7/24/24 9:15 AM, Christoph Müllner wrote: auto_inc_dec (-O3) performs optimizations like the following if RVV and XTheadMemIdx is enabled. (insn 23 20 27 3 (set (mem:V4QI (reg:DI 136 [ ivtmp.13 ]) [0 MEM [(char *)_39]+0 S4 A32]) (reg:V4QI 168))

[PATCH v2 2/3] aarch64: Add support for moving fpm system register

Unlike most system registers, fpmr can be heavily written to in code that exercises the fp8 functionality. That is because every fp8 instrinsic call can potentially change the value of fpmr. Rather than just use a an unspec, we treat the fpmr system register like all other registers and use a

[PATCH v2 3/3] aarch64: Add fpm register helper functions.

The ACLE declares several helper types and functions to facilitate construction of `fpm` arguments. gcc/ChangeLog: * config/aarch64/arm_acle.h (fpm_t): New type representing fpmr values. (enum __ARM_FPM_FORMAT): New enum representing valid fp8 formats. (enum

[PATCH v2 1/3] aarch64: Add march flags for +fp8 arch extensions

This introduces the relevant flags to enable access to the fpmr register and fp8 intrinsics, which will be added subsequently. gcc/ChangeLog: * config/aarch64/aarch64-option-extensions.def (fp8): New. * config/aarch64/aarch64.h (TARGET_FP8): Likewise. * doc/invoke.texi

[PATCH v2 0/3] aarch64: Add initial support for +fp8 arch extensions

Point Mode Register) which configures the new FP8 features Tested against aarch64-unknown-linux-gnu. V1 of this patch series had "aarch64: Add march flags for +fp8 arch extensions" as cover letter title. Since then, changes in V2 are: aarch64: Add march flags for +fp8 arch extensions

Re: [PATCH 2/2] cp+coroutines: teach convert_to_void to diagnose discarded co_awaits

On 7/24/24 4:52 PM, Arsen Arsenović wrote: Jason Merrill writes: Ah, of course, I was overlooking the assignment. The patch is OK. Thanks. Here's a range diff with a few changes to the commits, chiefly in the commit messages. If you agree, I can push with these changes applied: Looks

Re: [PATCH v3 01/12] OpenMP: metadirective tree data structures and front-end interfaces

Hi Sandra, thanks for your patch. (Disclaimer: I have not finished reading through your patch.) Some upfront generic remarks: [* When first compiling it (incremental build), I did run into the issue that OMP_METADIRECTIVE_CHECK wasn't declared. Thus, there seems to be a dependency issue

[PATCH] fold: Allow SSA names in inverse_conditions_p and fold VCOND_MASK.

Hi, In preparation for the maskload else operand I split off this patch. The patch looks through SSA names for the conditions passed to inverse_conditions_p which helps match.pd recognize more redundant vec_cond expressions. It also adds VCOND_MASK to the respective iterators in match.pd

[PATCH] tree-optimization/116083 - improve behavior when SLP discovery limit is reached

The following avoids some useless work when the SLP discovery limit is reached, for example allocating a node to cache the failure and starting discovery on split store groups when analyzing BBs. It does not address the issue in the PR which is a gratious budget for discovery when the store group

Re: [PATCH v2] RISC-V: Add basic support for the Zacas extension

On Tue, Jul 23, 2024 at 05:15:44PM -0700, Patrick O'Neill wrote: > From: Gianluca Guida > > This patch adds support for amocas.{b|h|w|d}. Support for amocas.q > (64/128 bit cas for rv32/64) will be added in a future patch. > > Extension: https://github.com/riscv/riscv-za

Re: [PATCH] aarch64: Fuse CMP+CSEL and CMP+CSET for -mcpu=neoverse-v2

e and if-then-else expressions. As it is not legal to >> have different modes in the operand registers, I only added one check for >> each of the expressions. >> The updated patch was bootstrapped and tested again. >> Best, >> Jennifer >> >> From 8da609be99f

Re: PING^3 [PATCH] rs6000: Adjust -fpatchable-function-entry* support for dual entry [PR112980]

Pinging this again. Em seg, 2024-07-22 às 17:18 +0800, Kewen.Lin escreveu: > Hi, > > Gentle ping this patch: > > https://gcc.gnu.org/pipermail/gcc-patches/2024-May/651025.html > > BR, > Kewen > > on 2024/7/12 00:15, Martin Jambor wrote: > > Hi, > > &

Re: [PATCH] doc: Document -O1 as the preferred level for large machine-generated code

On Tue, Jul 23, 2024 at 4:07 PM Sam James wrote: > > At -O1, the intention is that we compile things in a "reasonable" amount > of time (ditto memory use). In particular, we try to especially avoid > optimizations which scale poorly on pathological cases, as is the case > for large

Re: [PATCH] MATCH: add abs support for half float

ow. > I will change this. > > Thanks, > Kugan > > > > > > Thanks. > > > Kugan > > > > > > > > (like what is in gcc.dg/c11-floatn-3.c and others). > > > > > > > > Other than that it looks good but I can't approv

Re: [PATCH 5/5] MATCH: Add an alt pattern for ANDN and IORN with constants

On Thu, Jul 25, 2024 at 4:18 AM Andrew Pinski wrote: > > With constants we can match `~(a | CST)` into `CST & ~a`. > Likewise `~(a & CST)` into `CST | ~a`. > > Built and tested for aarch64-linux-gnu with no regressions. Similar, I think this should be in ISEL instead. > PR target/116013

Re: [PATCH 4/5] MATCH: Create BIT_ANDN and BIT_IORN from matching

On Thu, Jul 25, 2024 at 4:16 AM Andrew Pinski wrote: > > To better create rtl directly from gimple, we can use > these already internal functions from the gimple. > > That is simplify `a & ~b` into BIT_ANDN. > Likewise `a | ~b` into BIT_IORN. > We only want to do this late after vectorization as

Re: [PATCH] aarch64: Fuse CMP+CSEL and CMP+CSET for -mcpu=neoverse-v2

expressions. > The updated patch was bootstrapped and tested again. > Best, > Jennifer > > From 8da609be99fece8130cf1429bd938b2a26c6672b Mon Sep 17 00:00:00 2001 > From: Jennifer Schmitz > Date: Wed, 24 Jul 2024 06:13:59 -0700 > Subject: [PATCH] aarch64: Fuse CMP+CSEL and CMP+CSET

[PATCH] tree-optimization/116081 - typedef vs. non-typedef in vectorization

The following fixes the code generation difference when using a typedef for the scalar type. The issue is using a pointer equality test for an INTEGER_CST which fails when the types are different variants. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. PR

Re: [PATCH] c++/modules: Implement P2615 'Meaningful Exports' [PR107688]

; > OK for trunk. I've committed following patch to mark it as implemented: diff --git a/htdocs/projects/cxx-status.html b/htdocs/projects/cxx-status.html index 4f5def93..b25959b6 100644 --- a/htdocs/projects/cxx-status.html +++ b/htdocs/projects/cxx-status.html @@ -569,7 +569,7 @@

Re: [PATCH] doc: Document -O1 as the preferred level for large machine-generated code

Eric Gallager writes: > On Tue, Jul 23, 2024 at 10:07 AM Sam James wrote: >> >> At -O1, the intention is that we compile things in a "reasonable" amount >> of time (ditto memory use). In particular, we try to especially avoid >> optimizations which scale poorly on pathological cases, as is the

Re: [PATCH] libstdc++: fix uses of explicit object parameter [PR116038]

rence to) > the current class, appropriately qualified, rather than e.g. using > std::forward which preserves the deduced type. > > This patch corrects the existing problematic uses of explicit object > parameters in the library, all of which forward the parameter via > std::forwar

[PATCH] tree-optimization/116079 - store motion and clobbers

When we move a store out of an inner loop and remove a clobber in the process, analysis of the inner loop can run into the clobber via the meta-data and crash when accessing its basic-block. The following avoids this by clearing the VDEF which is how it identifies already processed stores.

[PATCH] tree-optimization/116081 - typedef vs. non-typedef in vectorization

The following addresses a behavioral difference in vector type analysis for typedef vs. non-typedef. It doesn't fix the issue at hand but avoids a spurious difference in the dumps. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. PR tree-optimization/116081 *

Re: [PATCH] libstdc++: Fix testsuite for remote testing (and sim)

On Thu, 25 Jul 2024 at 07:32, Jonathan Wakely wrote: > > > > On Thu, 25 Jul 2024, 02:58 Andrew Pinski, wrote: >> >> The problem here is that v3_additional_files will have a space >> at the begining of the string as dg-additional-files will append >> `" " $files` to it. Then when split is called

Re: [PATCH, gfortran] libgfortran: implement fpu-macppc for Darwin, support IEEE arithmetic

Can you post an updated version of the patch, following the first round of review? FX

Re: [PATCH] doc: Document -O1 as the preferred level for large machine-generated code

On Tue, Jul 23, 2024 at 10:07 AM Sam James wrote: > > At -O1, the intention is that we compile things in a "reasonable" amount > of time (ditto memory use). In particular, we try to especially avoid > optimizations which scale poorly on pathological cases, as is the case > for large

Re: [PATCH ver 2] rs6000, remove __builtin_vsx_xvcmp* built-ins

Hi Carl, on 2024/7/24 01:06, Carl Love wrote: > GCC maintainers: > > version 2, Updated patch comments, added missing ChangeLog.  Fixed unintended > line removal. > > The following patch removes the three __builtin_vsx_xvcmp[eq|ge|gt]sp  > builtins as they similar to the

Re: [PATCH 1/2] rs6000, Remove __builtin_vec_set_v1ti,, __builtin_vec_set_v2df, __builtin_vec_set_v2di

Hi Carl, on 2024/7/24 01:52, Carl Love wrote: > > GCC maintainers: > > This patch was previously posted.  Per the feedback, it is now the first of > two patches to remove the set built-ins. > > This patch removes the __builtin_vec_set_v1ti, __builtin_vec_set_v2df and >

Re: [PATCH 2/2] rs6000, remove built-ins __builtin_vsx_set_1ti, __builtin_vsx_set_2df, __builtin_vsx_set_2di

Hi Carl, on 2024/7/24 01:52, Carl Love wrote: > GCC maintainers: > > This patch removes the vsx set built-ins: __builtin_vsx_set_1ti, > __builtin_vsx_set_2df, __builtin_vsx_set_2di.  With the  removal of these > built-ins, the built-in attribute "set", used in the bu

Re: [PATCH 0/2] rs6000, remove vec and vsx set builtins

d for the built-ins for > both the -O0 and -O3 levels of optimization. > > For the vec_insert built-in bif whose resolving makes use of the vec_set bif > previously, is now removed, is as good as before with optimization. > > This two patch series removes the __builtin_vec_se

Re: [PATCH] rs6000, Add new overloaded vector shift builtin int128, varients

Hi Carl, Some minor comments are inlined on top of Segher's and Peter's comments. on 2024/7/20 04:04, Carl Love wrote: > GCC developers: > > The following patch adds the int128 varients to the existing overloaded > built-ins vec_sld, vec_sldb, vec_sldw, vec_sll, vec_slo, vec_s

Re: [PATCH] [x86]Refine constraint "Bk" to define_special_memory_constraint.

On Wed, Jul 24, 2024 at 3:57 PM liuhongt wrote: > > For below pattern, RA may still allocate r162 as v/k register, try to > reload for address with leaq __libc_tsd_CTYPE_B@gottpoff(%rip), %rsi > which result a linker error. > > (set (reg:DI 162) > (mem/u/c:DI >(const:DI (unspec:DI >

Re: [PATCH 2/5] aarch64: sve: Rename aarch64_bic to standard pattern, andn

> On 25 Jul 2024, at 04:14, Andrew Pinski wrote: > > External email: Use caution opening links or attachments > > > Now there is an optab for bic, andn since r15-1890-gf379596e0ba99d. > This moves aarch64_bic for sve over to use it instead. > > Note unlike the simd bic patterns, the

Re: [PATCH] SVE Intrinsics: Change return type of redirect_call to gcall.

> On 24 Jul 2024, at 18:50, Richard Sandiford wrote: > > External email: Use caution opening links or attachments > > > Jennifer Schmitz writes: >> As suggested in the review of >> https://gcc.gnu.org/pipermail/gcc-patches/2024-July/657474.html, >>

Re: [PATCH] libstdc++: Fix testsuite for remote testing (and sim)

On Thu, 25 Jul 2024, 02:58 Andrew Pinski, wrote: > The problem here is that v3_additional_files will have a space > at the begining of the string as dg-additional-files will append > `" " $files` to it. Then when split is called on that string, > there will be an empty file and copying a dir

Re: [PATCH 1/5] aarch64: Rename bic/orn patterns to iorn/andn for vector modes

t? Yes because currently the `(a > b) ? 0 : c` syntax is currently only supported with the C++ front-end. See https://gcc.gnu.org/pipermail/gcc-patches/2024-July/657682.html for the RFC patch to add it for the C front-end. Thanks, Andrew Pinski > Thanks, > Kyrill > > > >

Re: [PATCH 3/5] aarch64: Use iorn and andn standard pattern names for scalar modes

Hi Andrew, > On 25 Jul 2024, at 04:14, Andrew Pinski wrote: > > External email: Use caution opening links or attachments > > > Since r15-1890-gf379596e0ba99d, these are the new optabs. > So let's use these names for them. These will be used to > generate during expand from gimple in the next

Re: [PATCH 1/5] aarch64: Rename bic/orn patterns to iorn/andn for vector modes

> On 25 Jul 2024, at 04:14, Andrew Pinski wrote: > > External email: Use caution opening links or attachments > > > This renames the patterns orn3 to iorn3 so it > matches the new optab that was added with r15-1890-gf379596e0ba99d. > Likewise for bic3 to andn3. > > Note the operand 1 and

[PATCH, rs6000] Add const_vector into any_operand predicate

Hi, This patch add const_vector into any_operand predicate. From my understanding, any_operand should include all kinds of operands. The const_vector should be included. As emit_move_insn doesn't check the predicate, the const_vector is actually supported by vector mode move expand. So it should

[PATCH V3] fsra: gimple final sra pass for paramters and returns

could use the current SRA pass in a special mode right before GIMPLE->RTL expansion for the parameters/returns, and scalarize the access according to the incoming/outgoing registers. Some discussion in: https://gcc.gnu.org/pipermail/gcc-patches/2023-November/637935.html This patch adds a FI

Re: [PATCH] MATCH: add abs support for half float

t; > > Thanks, > > > Andrew Pinski > > > > > > > > > > > Signed-off-by: Kugan Vivekanandarajah > > > > > > > > Bootstrapped and regression test on aarch64-linux-gnu. Is this OK for > > > > trunk? > > > > Thanks, >

[PATCH 5/5] MATCH: Add an alt pattern for ANDN and IORN with constants

With constants we can match `~(a | CST)` into `CST & ~a`. Likewise `~(a & CST)` into `CST | ~a`. Built and tested for aarch64-linux-gnu with no regressions. PR target/116013 PR target/115086 gcc/ChangeLog: * match.pd (`~(a & CST)`, `~(a | CST)`): New pattern.

[PATCH 3/5] aarch64: Use iorn and andn standard pattern names for scalar modes

Since r15-1890-gf379596e0ba99d, these are the new optabs. So let's use these names for them. These will be used to generate during expand from gimple in the next few patches. Built and tested for aarch64-linux-gnu with no regressions. gcc/ChangeLog: * config/aarch64/aarch64.md

[PATCH 4/5] MATCH: Create BIT_ANDN and BIT_IORN from matching

To better create rtl directly from gimple, we can use these already internal functions from the gimple. That is simplify `a & ~b` into BIT_ANDN. Likewise `a | ~b` into BIT_IORN. We only want to do this late after vectorization as some targets (e.g. aarch64 SVE) has BIT_IORN on scalars but not on

[PATCH 2/5] aarch64: sve: Rename aarch64_bic to standard pattern, andn

Now there is an optab for bic, andn since r15-1890-gf379596e0ba99d. This moves aarch64_bic for sve over to use it instead. Note unlike the simd bic patterns, the operands were already in the order that was expected for the optab so no swapping was needed. Built and tested on aarch64-linux-gnu

[PATCH 1/5] aarch64: Rename bic/orn patterns to iorn/andn for vector modes

This renames the patterns orn3 to iorn3 so it matches the new optab that was added with r15-1890-gf379596e0ba99d. Likewise for bic3 to andn3. Note the operand 1 and operand 2 are swapped from the original patterns to match the optab now. Built and tested for aarch64-linux-gnu with no regression.

[PATCH] libstdc++: Fix testsuite for remote testing (and sim)

The problem here is that v3_additional_files will have a space at the begining of the string as dg-additional-files will append `" " $files` to it. Then when split is called on that string, there will be an empty file and copying a dir will just fail for remote/sim testing (I didn't look at why

Re: [PATCH 7/8] libstdc++: Stop copying all data files into test directory

sary files declared with dg-additional-files are > copied. Note one of these patches in this set broke testing in some cases. The reason is that v3_additional_files will be " file1 file2" and calling split on it, there will be an empty filename for the first entry.

Re: [PATCH] i386: Adjust rtx cost for imulq and imulw [PR115749]

On Wed, Jul 24, 2024 at 3:11 PM Kong, Lingling wrote: > > Tested spec2017 performance in Sierra Forest, Icelake, CascadeLake, at least > there is no obvious regression. > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. > > OK for trunk? Ok. > > gcc/ChangeLog: > > *

Re: [PATCH, gfortran] libgfortran: implement fpu-macppc for Darwin, support IEEE arithmetic

Bumping the topic. Since this patch exclusively affects powerpc-darwin, and I think we agree that it does not add regressions with tests (no tests which passed without it fail with it), perhaps it can be merged? It would be great to have it in gcc 15 when it is released, otherwise we will need

[PATCH] libstdc++: fix uses of explicit object parameter [PR116038]

low testcases. This pitfall is discussed[1] in the deducing this paper. The general solution is to cast the explicit object parameter to (a reference to) the current class, appropriately qualified, rather than e.g. using std::forward which preserves the deduced type. This patch corrects the exist

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