Re: [PATCH][AArch64] Add HF vector modes to lane-to-lane INS pattern

On Fri, Apr 21, 2017 at 09:34:20AM +0100, Kyrill Tkachov wrote: > Hi all, > > For the testcase in the patch we currently miss a combination and generate: > foo: > dup h1, v1.h[2] > ins v0.h[3], v1.h[0] > ret > > bar: > dup h1, v1.h[2] > ins

Re: [PATCH][AArch64] Add HF vector modes to lane-to-lane INS pattern

Ping. Thanks, Kyrill On 11/05/17 11:15, Kyrill Tkachov wrote: Ping. https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00933.html Thanks, Kyrill On 21/04/17 09:34, Kyrill Tkachov wrote: Hi all, For the testcase in the patch we currently miss a combination and generate: foo: dup h1,

Re: [PATCH][AArch64] Add HF vector modes to lane-to-lane INS pattern

Ping. https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00933.html Thanks, Kyrill On 21/04/17 09:34, Kyrill Tkachov wrote: Hi all, For the testcase in the patch we currently miss a combination and generate: foo: dup h1, v1.h[2] ins v0.h[3], v1.h[0] ret bar:

[PATCH][AArch64] Add HF vector modes to lane-to-lane INS pattern

Hi all, For the testcase in the patch we currently miss a combination and generate: foo: dup h1, v1.h[2] ins v0.h[3], v1.h[0] ret bar: dup h1, v1.h[2] ins v0.h[3], v1.h[0] ret This is because the *aarch64_simd_vec_copy_lane pattern