On 20 October 2015 at 17:26, Kyrill Tkachov wrote:
> Hi Marcus,
>
> On 20/10/15 17:05, Marcus Shawcroft wrote:
>>
>> On 16 October 2015 at 13:58, Kyrill Tkachov
>> wrote:
>>>
>>> Hi all,
>>>
>>> We already support load/store-pair operations on the D-registers when
>>> they
>>> contain an FP value
Hi Marcus,
On 20/10/15 17:05, Marcus Shawcroft wrote:
On 16 October 2015 at 13:58, Kyrill Tkachov wrote:
Hi all,
We already support load/store-pair operations on the D-registers when they
contain an FP value, but the peepholes/sched-fusion machinery that
do all the hard work currently ignore
On 16 October 2015 at 13:58, Kyrill Tkachov wrote:
> Hi all,
>
> We already support load/store-pair operations on the D-registers when they
> contain an FP value, but the peepholes/sched-fusion machinery that
> do all the hard work currently ignore 64-bit vector modes.
>
> This patch adds support
Hi all,
We already support load/store-pair operations on the D-registers when they
contain an FP value, but the peepholes/sched-fusion machinery that
do all the hard work currently ignore 64-bit vector modes.
This patch adds support for fusing loads/stores of 64-bit vector operands into
ldp an
