On Fri, Apr 27, 2018 at 09:29:28AM +0100, Kyrill Tkachov wrote:
>
> On 26/04/18 14:47, Richard Sandiford wrote:
> > Kyrill Tkachov writes:
> >> On 24/04/18 17:41, Jakub Jelinek wrote:
> >>> On Tue, Apr 24, 2018 at 05:22:15PM +0100, Kyrill Tkachov wrote:
> I've cleaned up the testcase a bit
On 26/04/18 14:47, Richard Sandiford wrote:
Kyrill Tkachov writes:
On 24/04/18 17:41, Jakub Jelinek wrote:
On Tue, Apr 24, 2018 at 05:22:15PM +0100, Kyrill Tkachov wrote:
I've cleaned up the testcase a bit to leave only the function that
generates the invalid instruction,
making it shorter.
Kyrill Tkachov writes:
> On 24/04/18 17:41, Jakub Jelinek wrote:
>> On Tue, Apr 24, 2018 at 05:22:15PM +0100, Kyrill Tkachov wrote:
>>> I've cleaned up the testcase a bit to leave only the function that
>>> generates the invalid instruction,
>>> making it shorter.
>>>
>>> Jakub, is the patch ok t
On Tue, Apr 24, 2018 at 05:22:15PM +0100, Kyrill Tkachov wrote:
> I've cleaned up the testcase a bit to leave only the function that generates
> the invalid instruction,
> making it shorter.
>
> Jakub, is the patch ok to go in for GCC 8 from your perspective?
The PR is marked P1 now, so sure, pl
On 24/04/18 17:41, Jakub Jelinek wrote:
On Tue, Apr 24, 2018 at 05:22:15PM +0100, Kyrill Tkachov wrote:
I've cleaned up the testcase a bit to leave only the function that generates
the invalid instruction,
making it shorter.
Jakub, is the patch ok to go in for GCC 8 from your perspective?
Th
On 24/04/18 17:09, James Greenhalgh wrote:
On Tue, Apr 24, 2018 at 04:38:31PM +0100, Kyrill Tkachov wrote:
Hi all,
In this testcase it is possible to generate an invalid SISD shift of zero:
Error: immediate value out of range 1 to 64 at operand 3 -- `sshr v9.2s,v0.2s,0'
The SSHR and USHR inst
On Tue, Apr 24, 2018 at 04:38:31PM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> In this testcase it is possible to generate an invalid SISD shift of zero:
> Error: immediate value out of range 1 to 64 at operand 3 -- `sshr
> v9.2s,v0.2s,0'
>
> The SSHR and USHR instructions require a shift from 1
Hi all,
In this testcase it is possible to generate an invalid SISD shift of zero:
Error: immediate value out of range 1 to 64 at operand 3 -- `sshr v9.2s,v0.2s,0'
The SSHR and USHR instructions require a shift from 1 up to the element size.
However our constraints on the scalar shifts that gene
