Th 11/14/2017 17:48, James Greenhalgh wrote:
> On Tue, Nov 14, 2017 at 04:05:12PM +, Tamar Christina wrote:
> > Hi James,
> >
> > I have split off the aarch64 bit off from the generic parts and processed
> > your feedback.
> >
> > Attached is the reworked patch.
> >
> > Ok for Tunk?
>
> Th
On Tue, Nov 14, 2017 at 04:05:12PM +, Tamar Christina wrote:
> Hi James,
>
> I have split off the aarch64 bit off from the generic parts and processed
> your feedback.
>
> Attached is the reworked patch.
>
> Ok for Tunk?
Thanks for the respin, I'm a bit confused by this comment.
> diff --
C Patches patc...@gcc.gnu.org>; nd ; Richard Earnshaw
> ; Marcus Shawcroft
>
> Subject: Re: [PATCH][GCC][AARCH64]Bad code-gen for
> structure/block/unaligned memory access
>
> Hi Tamar,
>
> I think the AArch64 parts of this patch can be substantially simplified.
>
Hi Tamar,
I think the AArch64 parts of this patch can be substantially simplified.
On Mon, Jul 03, 2017 at 07:17:51AM +0100, Tamar Christina wrote:
> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
> index
> ab1bdc0233afe7a3c41501cb724a5c4c719123b8..1cf6c4b891571745f740d
t: Re: [PATCH][GCC][AARCH64]Bad code-gen for structure/block/unaligned
memory access
On Wed, Aug 30, 2017 at 2:21 AM, Tamar Christina
wrote:
> Hi,
>
> The test I used was testsuite/gcc.c-torture/compile/structs.c
Results look very nice on x86-64. Can we add a testcase to scan the
compiler ou
nks,
> Tamar
>
> From: H.J. Lu
> Sent: Friday, August 25, 2017 8:10:22 PM
> To: Tamar Christina
> Cc: Richard Sandiford; GCC Patches; nd; James Greenhalgh; Richard Earnshaw;
> Marcus Shawcroft
> Subject: Re: [PATCH][GCC][AARCH64]Bad code-gen for structure/blo
Subject: Re: [PATCH][GCC][AARCH64]Bad code-gen for structure/block/unaligned
memory access
On Sun, Jul 2, 2017 at 11:17 PM, Tamar Christina
wrote:
> Hi All,
>
> Sorry I just realized I never actually sent the updated patch...
>
> So here it is :)
>
Are there any testcases?
--
H.J.
On Sun, Jul 2, 2017 at 11:17 PM, Tamar Christina
wrote:
> Hi All,
>
> Sorry I just realized I never actually sent the updated patch...
>
> So here it is :)
>
Are there any testcases?
--
H.J.
> From: gcc-patches-ow...@gcc.gnu.org on behalf
> of Tamar Christina
> Sent: Friday, June 9, 2017 4:51:52 PM
> To: Richard Sandiford
> Cc: GCC Patches; nd; James Greenhalgh; Richard Earnshaw; Marcus Shawcroft
> Subject: RE: [PATCH][GCC][AA
; James Greenhalgh; Richard Earnshaw; Marcus Shawcroft
Subject: RE: [PATCH][GCC][AARCH64]Bad code-gen for structure/block/unaligned
memory access
> > + /* Optimize routines for MEM to REG copies. */ if (n < 8 &&
> > + !REG_P (XEXP (operands[0], 0)))
>
> This seems to
> > + /* Optimize routines for MEM to REG copies. */ if (n < 8 &&
> > + !REG_P (XEXP (operands[0], 0)))
>
> This seems to be checking that the address of the original destination
> memory isn't a plain base register. Why's it important to reject that case
> but
> allow e.g. base+offset?
thi
> > + /* Optimize routines for MEM to REG copies. */ if (n < 8 &&
> > + !REG_P (XEXP (operands[0], 0)))
>
> This seems to be checking that the address of the original destination
> memory isn't a plain base register. Why's it important to reject that case
> but
> allow e.g. base+offset?
>
I
Tamar Christina writes:
> Hi All,
>
> This patch allows larger bitsizes to be used as copy size
> when the target does not have SLOW_UNALIGNED_ACCESS.
>
> It also provides an optimized routine for MEM to REG
> copying which avoid reconstructing the value piecewise on the stack
> and instead uses
Hi All,
This patch allows larger bitsizes to be used as copy size
when the target does not have SLOW_UNALIGNED_ACCESS.
It also provides an optimized routine for MEM to REG
copying which avoid reconstructing the value piecewise on the stack
and instead uses a combination of shifts and ORs.
This
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