Hello,
This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo
hard-register and also
.save {ra_auth_code} and .cfi_offset ra_auth_code <offset> dwarf directives for
the PAC feature
in Armv8.1-M architecture.
RA_AUTH_CODE register number is 107 and it's dwarf register number is 143.
When compiled with "arm-none-eabi-gcc -O2 -mthumb -march=armv8.1-m.main+pacbti
-S -fasynchronous-unwind-tables -g"
command line options, the directives supported in this patch looks like below:
...
push {ip}
.save {ra_auth_code}
.cfi_def_cfa_offset 8
.cfi_offset 143, -8
...
This patch can be committed after the patch at
https://gcc.gnu.org/pipermail/gcc-patches/2021-November/583407.html
is committed.
Regression tested on arm-none-eabi target and found no regressions.
Ok for master?
Regards,
Srinath.
gcc/ChangeLog:
2021-11-12 Srinath Parvathaneni <srinath.parvathan...@arm.com>
* config/arm/aout.h (ra_auth_code): Add to enum.
* config/arm/arm.c (emit_multi_reg_push): Add RA_AUTH_CODE register to
dwarf frame expression instead of IP_REGNUM.
(arm_expand_prologue): Mark as frame related insn.
(arm_regno_class): Check for pac pseudo reigster.
(arm_dbx_register_number): Assign ra_auth_code register number in dwarf.
(arm_unwind_emit_sequence): Print .save directive with ra_auth_code
register.
(arm_conditional_register_usage): Mark ra_auth_code in fixed reigsters.
* config/arm/arm.h (FIRST_PSEUDO_REGISTER): Modify.
(IS_PAC_Pseudo_REGNUM): Define.
(enum reg_class): Add PAC_REG entry.
* config/arm/arm.md (RA_AUTH_CODE): Define.
gcc/testsuite/ChangeLog:
2021-11-12 Srinath Parvathaneni <srinath.parvathan...@arm.com>
* gcc.target/arm/pac-6.c: New test.
############### Attachment also inlined for ease of reply ###############
diff --git a/gcc/config/arm/aout.h b/gcc/config/arm/aout.h
index
25a2812a663742893b928398b0d3948e97f1905b..c69e299e012f46c8d0711830125dbf2f6b2e93d7
100644
--- a/gcc/config/arm/aout.h
+++ b/gcc/config/arm/aout.h
@@ -74,7 +74,8 @@
"wr8", "wr9", "wr10", "wr11", \
"wr12", "wr13", "wr14", "wr15", \
"wcgr0", "wcgr1", "wcgr2", "wcgr3", \
- "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0" \
+ "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0", \
+ "ra_auth_code" \
}
#endif
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index
8e6ef41f6b065217d1af3f4f1cb85b2d8fbd0dc0..f31944e85c9ab83501f156d138e2aea1bcb5b79d
100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -815,7 +815,8 @@ extern const int arm_arch_cde_coproc_bits[];
s16-s31 S VFP variable (aka d8-d15).
vfpcc Not a real register. Represents the VFP condition
code flags.
- vpr Used to represent MVE VPR predication. */
+ vpr Used to represent MVE VPR predication.
+ ra_auth_code Pseudo register to save PAC. */
/* The stack backtrace structure is as follows:
fp points to here: | save code pointer | [fp]
@@ -856,7 +857,7 @@ extern const int arm_arch_cde_coproc_bits[];
1,1,1,1,1,1,1,1, \
1,1,1,1, \
/* Specials. */ \
- 1,1,1,1,1,1,1 \
+ 1,1,1,1,1,1,1,1 \
}
/* 1 for registers not available across function calls.
@@ -886,7 +887,7 @@ extern const int arm_arch_cde_coproc_bits[];
1,1,1,1,1,1,1,1, \
1,1,1,1, \
/* Specials. */ \
- 1,1,1,1,1,1,1 \
+ 1,1,1,1,1,1,1,1 \
}
#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
@@ -1062,10 +1063,10 @@ extern const int arm_arch_cde_coproc_bits[];
&& (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
/* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP
- + 1 APSRQ + 1 APSRGE + 1 VPR. */
+ + 1 APSRQ + 1 APSRGE + 1 VPR + 1 Pseudo register to save PAC. */
/* Intel Wireless MMX Technology registers add 16 + 4 more. */
/* VFP (VFP3) adds 32 (64) + 1 VFPCC. */
-#define FIRST_PSEUDO_REGISTER 107
+#define FIRST_PSEUDO_REGISTER 108
#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
@@ -1248,12 +1249,15 @@ extern int arm_regs_in_sequence[];
CC_REGNUM, VFPCC_REGNUM, \
FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \
SP_REGNUM, PC_REGNUM, APSRQ_REGNUM, \
- APSRGE_REGNUM, VPR_REGNUM \
+ APSRGE_REGNUM, VPR_REGNUM, RA_AUTH_CODE \
}
#define IS_VPR_REGNUM(REGNUM) \
((REGNUM) == VPR_REGNUM)
+#define IS_PAC_Pseudo_REGNUM(REGNUM) \
+ ((REGNUM) == RA_AUTH_CODE)
+
/* Use different register alloc ordering for Thumb. */
#define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
@@ -1292,6 +1296,7 @@ enum reg_class
SFP_REG,
AFP_REG,
VPR_REG,
+ PAC_REG,
ALL_REGS,
LIM_REG_CLASSES
};
@@ -1321,6 +1326,7 @@ enum reg_class
"SFP_REG", \
"AFP_REG", \
"VPR_REG", \
+ "PAC_REG", \
"ALL_REGS" \
}
@@ -1349,6 +1355,7 @@ enum reg_class
{ 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000400 }, /* VPR_REG. */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000800 }, /* PAC_REG. */ \
{ 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS. */ \
}
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index
a3e34747ba52840bd82f76df4a3f05704bd42ec1..966c49a3bf21de909dbab5abcac5d1d3b2af4262
100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -22000,7 +22000,9 @@ emit_multi_reg_push (unsigned long mask, unsigned long
dwarf_regs_mask)
{
if (mask & (1 << i))
{
- reg = gen_rtx_REG (SImode, i);
+ rtx reg1 = reg = gen_rtx_REG (SImode, i);
+ if (arm_pac_enabled_for_curr_function_p () && i == IP_REGNUM)
+ reg1 = gen_rtx_REG (SImode, RA_AUTH_CODE);
XVECEXP (par, 0, 0)
= gen_rtx_SET (gen_frame_mem
@@ -22018,7 +22020,7 @@ emit_multi_reg_push (unsigned long mask, unsigned long
dwarf_regs_mask)
if (dwarf_regs_mask & (1 << i))
{
tmp = gen_rtx_SET (gen_frame_mem (SImode, stack_pointer_rtx),
- reg);
+ reg1);
RTX_FRAME_RELATED_P (tmp) = 1;
XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
}
@@ -23505,7 +23507,10 @@ arm_expand_prologue (void)
saved_regs += arm_save_coproc_regs ();
if (arm_pac_enabled_for_curr_function_p ())
- emit_multi_reg_push (1 << IP_REGNUM, 1 << IP_REGNUM);
+ {
+ insn = emit_multi_reg_push (1 << IP_REGNUM, 1 << IP_REGNUM);
+ RTX_FRAME_RELATED_P (insn) = 1;
+ }
if (frame_pointer_needed && TARGET_ARM)
{
@@ -25435,6 +25440,9 @@ arm_regno_class (int regno)
if (IS_VPR_REGNUM (regno))
return VPR_REG;
+ if (IS_PAC_Pseudo_REGNUM (regno))
+ return PAC_REG;
+
if (TARGET_THUMB1)
{
if (regno == STACK_POINTER_REGNUM)
@@ -29429,6 +29437,9 @@ arm_dbx_register_number (unsigned int regno)
if (IS_IWMMXT_REGNUM (regno))
return 112 + regno - FIRST_IWMMXT_REGNUM;
+ if (IS_PAC_Pseudo_REGNUM (regno))
+ return 143;
+
return DWARF_FRAME_REGISTERS;
}
@@ -29550,6 +29561,11 @@ arm_unwind_emit_sequence (FILE * out_file, rtx p)
reg_size = 8;
fprintf (out_file, "\t.vsave {");
}
+ else if (IS_PAC_Pseudo_REGNUM (reg))
+ {
+ reg_size = 4;
+ fprintf (out_file, "\t.save {");
+ }
else
/* Unknown register type. */
gcc_unreachable ();
@@ -29579,6 +29595,8 @@ arm_unwind_emit_sequence (FILE * out_file, rtx p)
double precision register names. */
if (IS_VFP_REGNUM (reg))
asm_fprintf (out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2);
+ else if (IS_PAC_Pseudo_REGNUM (reg))
+ asm_fprintf (asm_out_file, "ra_auth_code");
else
asm_fprintf (out_file, "%r", reg);
@@ -30447,7 +30465,10 @@ arm_conditional_register_usage (void)
}
if (TARGET_HAVE_PACBTI)
- call_used_regs[IP_REGNUM] = 1;
+ {
+ call_used_regs[IP_REGNUM] = 1;
+ fixed_regs[RA_AUTH_CODE] = 0;
+ }
/* The Q and GE bits are only accessed via special ACLE patterns. */
CLEAR_HARD_REG_BIT (operand_reg_set, APSRQ_REGNUM);
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index
564170dc4500c2c5d961c9a19dd86a31416dc965..f27dc3f9041d8b32e7ad750c39143a6764156fe9
100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -42,6 +42,7 @@
(APSRQ_REGNUM 104) ; Q bit pseudo register
(APSRGE_REGNUM 105) ; GE bits pseudo register
(VPR_REGNUM 106) ; Vector Predication Register - MVE register.
+ (RA_AUTH_CODE 107) ; Pseudo register to save PAC.
]
)
;; 3rd operand to select_dominance_cc_mode
diff --git a/gcc/testsuite/gcc.target/arm/pac-6.c
b/gcc/testsuite/gcc.target/arm/pac-6.c
new file mode 100644
index
0000000000000000000000000000000000000000..25d6ae520aa1cece6a572c1d643fd640053106d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pac-6.c
@@ -0,0 +1,31 @@
+/* Check that GCC does .save and .cfi_offset directives with RA_AUTH_CODE
pseudo hard-register. */
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
+/* { dg-options "-march=armv8.1-m.main -mbranch-protection=pac-ret+leaf
-mthumb -mfloat-abi=softfp --save-temps -O2 -fasynchronous-unwind-tables -g" }
*/
+
+#include <stdio.h>
+#define ARM_UNWIND_INFO
+
+struct name {
+ int a;
+ char b;
+} list;
+
+void func (struct name list);
+
+int main()
+{
+ list.a = 10;
+ list.b = 'c';
+ func (list);
+ return 0;
+}
+
+void func (struct name list)
+{
+ printf ("list.d = %d\n", list.a);
+ printf ("list.b = %c\n", list.b);
+}
+
+/* { dg-final { scan-assembler "\.save \{ra_auth_code\}" } } */
+/* { dg-final { scan-assembler "\.cfi_offset 143, \-8" } } */
diff --git a/gcc/config/arm/aout.h b/gcc/config/arm/aout.h
index
25a2812a663742893b928398b0d3948e97f1905b..c69e299e012f46c8d0711830125dbf2f6b2e93d7
100644
--- a/gcc/config/arm/aout.h
+++ b/gcc/config/arm/aout.h
@@ -74,7 +74,8 @@
"wr8", "wr9", "wr10", "wr11", \
"wr12", "wr13", "wr14", "wr15", \
"wcgr0", "wcgr1", "wcgr2", "wcgr3", \
- "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0" \
+ "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0", \
+ "ra_auth_code" \
}
#endif
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index
8e6ef41f6b065217d1af3f4f1cb85b2d8fbd0dc0..f31944e85c9ab83501f156d138e2aea1bcb5b79d
100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -815,7 +815,8 @@ extern const int arm_arch_cde_coproc_bits[];
s16-s31 S VFP variable (aka d8-d15).
vfpcc Not a real register. Represents the VFP condition
code flags.
- vpr Used to represent MVE VPR predication. */
+ vpr Used to represent MVE VPR predication.
+ ra_auth_code Pseudo register to save PAC. */
/* The stack backtrace structure is as follows:
fp points to here: | save code pointer | [fp]
@@ -856,7 +857,7 @@ extern const int arm_arch_cde_coproc_bits[];
1,1,1,1,1,1,1,1, \
1,1,1,1, \
/* Specials. */ \
- 1,1,1,1,1,1,1 \
+ 1,1,1,1,1,1,1,1 \
}
/* 1 for registers not available across function calls.
@@ -886,7 +887,7 @@ extern const int arm_arch_cde_coproc_bits[];
1,1,1,1,1,1,1,1, \
1,1,1,1, \
/* Specials. */ \
- 1,1,1,1,1,1,1 \
+ 1,1,1,1,1,1,1,1 \
}
#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
@@ -1062,10 +1063,10 @@ extern const int arm_arch_cde_coproc_bits[];
&& (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
/* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP
- + 1 APSRQ + 1 APSRGE + 1 VPR. */
+ + 1 APSRQ + 1 APSRGE + 1 VPR + 1 Pseudo register to save PAC. */
/* Intel Wireless MMX Technology registers add 16 + 4 more. */
/* VFP (VFP3) adds 32 (64) + 1 VFPCC. */
-#define FIRST_PSEUDO_REGISTER 107
+#define FIRST_PSEUDO_REGISTER 108
#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
@@ -1248,12 +1249,15 @@ extern int arm_regs_in_sequence[];
CC_REGNUM, VFPCC_REGNUM, \
FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \
SP_REGNUM, PC_REGNUM, APSRQ_REGNUM, \
- APSRGE_REGNUM, VPR_REGNUM \
+ APSRGE_REGNUM, VPR_REGNUM, RA_AUTH_CODE \
}
#define IS_VPR_REGNUM(REGNUM) \
((REGNUM) == VPR_REGNUM)
+#define IS_PAC_Pseudo_REGNUM(REGNUM) \
+ ((REGNUM) == RA_AUTH_CODE)
+
/* Use different register alloc ordering for Thumb. */
#define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
@@ -1292,6 +1296,7 @@ enum reg_class
SFP_REG,
AFP_REG,
VPR_REG,
+ PAC_REG,
ALL_REGS,
LIM_REG_CLASSES
};
@@ -1321,6 +1326,7 @@ enum reg_class
"SFP_REG", \
"AFP_REG", \
"VPR_REG", \
+ "PAC_REG", \
"ALL_REGS" \
}
@@ -1349,6 +1355,7 @@ enum reg_class
{ 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000400 }, /* VPR_REG. */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000800 }, /* PAC_REG. */ \
{ 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS. */ \
}
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index
a3e34747ba52840bd82f76df4a3f05704bd42ec1..966c49a3bf21de909dbab5abcac5d1d3b2af4262
100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -22000,7 +22000,9 @@ emit_multi_reg_push (unsigned long mask, unsigned long
dwarf_regs_mask)
{
if (mask & (1 << i))
{
- reg = gen_rtx_REG (SImode, i);
+ rtx reg1 = reg = gen_rtx_REG (SImode, i);
+ if (arm_pac_enabled_for_curr_function_p () && i == IP_REGNUM)
+ reg1 = gen_rtx_REG (SImode, RA_AUTH_CODE);
XVECEXP (par, 0, 0)
= gen_rtx_SET (gen_frame_mem
@@ -22018,7 +22020,7 @@ emit_multi_reg_push (unsigned long mask, unsigned long
dwarf_regs_mask)
if (dwarf_regs_mask & (1 << i))
{
tmp = gen_rtx_SET (gen_frame_mem (SImode, stack_pointer_rtx),
- reg);
+ reg1);
RTX_FRAME_RELATED_P (tmp) = 1;
XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
}
@@ -23505,7 +23507,10 @@ arm_expand_prologue (void)
saved_regs += arm_save_coproc_regs ();
if (arm_pac_enabled_for_curr_function_p ())
- emit_multi_reg_push (1 << IP_REGNUM, 1 << IP_REGNUM);
+ {
+ insn = emit_multi_reg_push (1 << IP_REGNUM, 1 << IP_REGNUM);
+ RTX_FRAME_RELATED_P (insn) = 1;
+ }
if (frame_pointer_needed && TARGET_ARM)
{
@@ -25435,6 +25440,9 @@ arm_regno_class (int regno)
if (IS_VPR_REGNUM (regno))
return VPR_REG;
+ if (IS_PAC_Pseudo_REGNUM (regno))
+ return PAC_REG;
+
if (TARGET_THUMB1)
{
if (regno == STACK_POINTER_REGNUM)
@@ -29429,6 +29437,9 @@ arm_dbx_register_number (unsigned int regno)
if (IS_IWMMXT_REGNUM (regno))
return 112 + regno - FIRST_IWMMXT_REGNUM;
+ if (IS_PAC_Pseudo_REGNUM (regno))
+ return 143;
+
return DWARF_FRAME_REGISTERS;
}
@@ -29550,6 +29561,11 @@ arm_unwind_emit_sequence (FILE * out_file, rtx p)
reg_size = 8;
fprintf (out_file, "\t.vsave {");
}
+ else if (IS_PAC_Pseudo_REGNUM (reg))
+ {
+ reg_size = 4;
+ fprintf (out_file, "\t.save {");
+ }
else
/* Unknown register type. */
gcc_unreachable ();
@@ -29579,6 +29595,8 @@ arm_unwind_emit_sequence (FILE * out_file, rtx p)
double precision register names. */
if (IS_VFP_REGNUM (reg))
asm_fprintf (out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2);
+ else if (IS_PAC_Pseudo_REGNUM (reg))
+ asm_fprintf (asm_out_file, "ra_auth_code");
else
asm_fprintf (out_file, "%r", reg);
@@ -30447,7 +30465,10 @@ arm_conditional_register_usage (void)
}
if (TARGET_HAVE_PACBTI)
- call_used_regs[IP_REGNUM] = 1;
+ {
+ call_used_regs[IP_REGNUM] = 1;
+ fixed_regs[RA_AUTH_CODE] = 0;
+ }
/* The Q and GE bits are only accessed via special ACLE patterns. */
CLEAR_HARD_REG_BIT (operand_reg_set, APSRQ_REGNUM);
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index
564170dc4500c2c5d961c9a19dd86a31416dc965..f27dc3f9041d8b32e7ad750c39143a6764156fe9
100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -42,6 +42,7 @@
(APSRQ_REGNUM 104) ; Q bit pseudo register
(APSRGE_REGNUM 105) ; GE bits pseudo register
(VPR_REGNUM 106) ; Vector Predication Register - MVE register.
+ (RA_AUTH_CODE 107) ; Pseudo register to save PAC.
]
)
;; 3rd operand to select_dominance_cc_mode
diff --git a/gcc/testsuite/gcc.target/arm/pac-6.c
b/gcc/testsuite/gcc.target/arm/pac-6.c
new file mode 100644
index
0000000000000000000000000000000000000000..25d6ae520aa1cece6a572c1d643fd640053106d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pac-6.c
@@ -0,0 +1,31 @@
+/* Check that GCC does .save and .cfi_offset directives with RA_AUTH_CODE
pseudo hard-register. */
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
+/* { dg-options "-march=armv8.1-m.main -mbranch-protection=pac-ret+leaf
-mthumb -mfloat-abi=softfp --save-temps -O2 -fasynchronous-unwind-tables -g" }
*/
+
+#include <stdio.h>
+#define ARM_UNWIND_INFO
+
+struct name {
+ int a;
+ char b;
+} list;
+
+void func (struct name list);
+
+int main()
+{
+ list.a = 10;
+ list.b = 'c';
+ func (list);
+ return 0;
+}
+
+void func (struct name list)
+{
+ printf ("list.d = %d\n", list.a);
+ printf ("list.b = %c\n", list.b);
+}
+
+/* { dg-final { scan-assembler "\.save \{ra_auth_code\}" } } */
+/* { dg-final { scan-assembler "\.cfi_offset 143, \-8" } } */
