Hi!
As the testcases show, dr_explicit_realign_optimized (used on PowerPC/SPU
only) misbehaves if the base_address is in between 1 and vector element size - 1
modulo vector size.
The problem is that it wants to add a bias to base_addr such that
base_addr & ~vector_size
(base_addr + bias) & ~vector
On Thu, 25 Sep 2014, Jakub Jelinek wrote:
> Hi!
>
> As the testcases show, dr_explicit_realign_optimized (used on PowerPC/SPU
> only) misbehaves if the base_address is in between 1 and vector element size
> - 1
> modulo vector size.
> The problem is that it wants to add a bias to base_addr such