On 22 July 2013 21:16, Eric Botcazou ebotca...@adacore.com wrote:
And if df_live is non-zero, do we need update df_lr's IN and OUT? I think
we need another patch to make all these consistency.
Possibly, but this would belong to another patch. I nevertheless think that
we
should set the bit
On 22 July 2013 17:56, Eric Botcazou ebotca...@adacore.com wrote:
The patch is updated based the comments: it will check GEN set of LIVE
if df_live exists. Otherwise, just give up.
The patch is missing a ChangeLog. Otherwise it looks good, modulo:
+ /* DF_LR_BB_INFO (bb)-def does
And if df_live is non-zero, do we need update df_lr's IN and OUT? I think
we need another patch to make all these consistency.
Possibly, but this would belong to another patch. I nevertheless think that we
should set the bit in the GEN set because we'll be testing the GEN set now.
The patch
Shrink-wrap optimization sinks some instructions for more
opportunities. It uses DF_LR_BB_INFO (bb)-def to check whether BB
clobbers SRC. But for ARM, gcc might generate cond_exec insns before
shrink-wrapping. And DF_LR_BB_INFO (bb)-def does not include def info
from cond_exec insns. So the
Ping?
Thanks!
-Zhenqiang
On 5 July 2013 17:37, Zhenqiang Chen zhenqiang.c...@linaro.org wrote:
On 5 July 2013 16:18, Jakub Jelinek ja...@redhat.com wrote:
On Fri, Jul 05, 2013 at 04:11:00PM +0800, Zhenqiang Chen wrote:
+ FOR_BB_INSNS(bb, x)
Just style nits:
Missing space between (.
Hi,
The patch is updated. If there is no df_live, we still can not
guarantee the correctness. So the new patch just checks the
DF_INSN_DEFS.
Bootstrap and no make check regression on x86-64.
Bootstrap on ARM chrome book.
Is it OK?
Thanks!
-Zhenqiang
Changelog:
2013-07-05 Zhenqiang Chen
On 5 July 2013 16:18, Jakub Jelinek ja...@redhat.com wrote:
On Fri, Jul 05, 2013 at 04:11:00PM +0800, Zhenqiang Chen wrote:
+ FOR_BB_INSNS(bb, x)
Just style nits:
Missing space between (. Also, please don't use uppercase names
for labels.
Jakub
Thanks for the comments.
On 27 June 2013 21:10, Richard Earnshaw rearn...@arm.com wrote:
On 27/06/13 10:02, Zhenqiang Chen wrote:
Hi,
Shrink-wrap optimization sinks some instructions for more
opportunities. It uses DF_LR_BB_INFO (bb)-def to check whether BB
clobbers SRC. But for ARM, gcc might generate cond_exec
Hi,
Shrink-wrap optimization sinks some instructions for more
opportunities. It uses DF_LR_BB_INFO (bb)-def to check whether BB
clobbers SRC. But for ARM, gcc might generate cond_exec insns before
shrink-wrapping. And DF_LR_BB_INFO (bb)-def does not include def info
from cond_exec insns. So the
On 27/06/13 10:02, Zhenqiang Chen wrote:
Hi,
Shrink-wrap optimization sinks some instructions for more
opportunities. It uses DF_LR_BB_INFO (bb)-def to check whether BB
clobbers SRC. But for ARM, gcc might generate cond_exec insns before
shrink-wrapping. And DF_LR_BB_INFO (bb)-def does not
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