On Sat, Apr 20, 2019 at 2:54 PM Vladimir Makarov <vmaka...@redhat.com> wrote:
>
>
> On 4/20/19 4:55 AM, Uros Bizjak wrote:
> > On 4/20/19, Vladimir Makarov <vmaka...@redhat.com> wrote:
> >> On 11/21/18 2:33 PM, Uros Bizjak wrote:
> >>> Hello!
> >>>
> >>> Before the recent patch to post-reload mode switching, vzeroupper
> >>> insertion depended on the existence of the return copy instructions
> >>> pair in functions that return a value. The first instruction in the
> >>> pair represents a move to a function return hard register, and the
> >>> second was a USE of the function return hard register. Sometimes a nop
> >>> move was generated (e.g. %eax->%eax) for the first instruction of the
> >>> return copy instructions pair and the patch [1] teached LRA to remove
> >>> these useless instructions on the fly.
> >>>
> >>> The removal caused optimize mode switching to trigger the assert,
> >>> since the first instruction of a return pair was not found. The
> >>> relevant part of the patch was later reverted. With the recent
> >>> optimize mode switching patch, this is no longer necessary for
> >>> vzeroupper insertion pass, so attached patch reverts the revert.
> >>>
> >>> 2018-11-21 Uros Bizjak <ubiz...@gmail.com>
> >>>
> >>> Revert the revert:
> >>> 2013-10-26 Vladimir Makarov <vmaka...@redhat.com>
> >>>
> >>> Revert:
> >>> 2013-10-25 Vladimir Makarov <vmaka...@redhat.com>
> >>>
> >>> * lra-spills.c (lra_final_code_change): Remove useless move insns.
> >>>
> >>> Patch was bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
> >>>
> >>> OK for mainline?
> >> Sure, Uros. I support the patch. But I think it would be wise to
> >> postpone its committing after releasing GCC-9. Simply it is hard to
> >> predict the patch effect to other targets and I would avoid any risk at
> >> this stage.
> > Actually, the "revert of the revert" patch was already committed to
> > mainline some time ago.
>
> Sorry for confusion, Uros. I did not check the date of your original
> posting. Insn removal was added to RA just to avoid wasting CPU cycles
> on such insn processing afterwards. Such insns are removed anyway later
> in the pass pipeline. The CPU time savings are tiny but the removal
> creates too many problems including new one PR90178. I should have
> avoided to put this code in the first place.
>
> I think we should remove this code forever. It is not convenient for me
> to do this now because I am traveling. If somebody wants to remove the
> code, i am approving this in advance.
I am checking in this patch.
Thanks.
>
> > To clear the possible misunderstanding, let me summarise the issue:
> >
> > - the original patch that remove useless move insn caused a breakage
> > in vzeroupper pass.
> > - the original patch was reverted due to the above breakage
> > - the vzeroupper pass was later adjusted to tolerate removed useless
> > move instructions, and this cleared the way to revert the revert. Now
> > LRA removes useless move insns.
> >
> > An orthogonal issue (PR90178) was discovered, showing that some passes
> > also depend on the presence of useless move insn.
> >
> > The bisection stumbled on the "revert of the revert" patch that
> > (obviously) re-introduced the issue. I'm not in the position to decide
> > if useless move insn can be removed or if these later passes should be
> > fixed, I can only say that the vzeroupper pass is now agnostic to the
> > presence of useless move insns.
> >
> > Uros.
--
H.J.
From ec029333fe6b3bed32c72dd4192c54a005e3fcb3 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Sun, 21 Apr 2019 11:00:24 -0700
Subject: [PATCH] LRA: Revert "Remove useless move insns"
Useless move insn removal was added to LRA just to avoid wasting CPU
cycles on such insn processing afterwards. Such insns are removed
anyway later in the pass pipeline. The CPU time savings are tiny but
the removal creates too many problems including PR target/90178.
Vladimir pre-approved the patch to remove the code:
https://gcc.gnu.org/ml/gcc-patches/2019-04/msg00834.html
gcc/
PR target/90178
Revert:
2018-11-21 Uros Bizjak <ubizjak@gmail.com>
Revert the revert:
2013-10-26 Vladimir Makarov <vmakarov@redhat.com>
Revert:
2013-10-25 Vladimir Makarov <vmakarov@redhat.com>
* lra-spills.c (lra_final_code_change): Remove useless move insns.
gcc/testsuite/
PR target/90178
* gcc.target/i386/pr90178.c: New test.
---
gcc/ChangeLog | 14 ++++++++++++++
gcc/lra-spills.c | 15 ---------------
gcc/testsuite/ChangeLog | 5 +++++
gcc/testsuite/gcc.target/i386/pr90178.c | 13 +++++++++++++
4 files changed, 32 insertions(+), 15 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/pr90178.c
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8b09eecfbfe..d2446815605 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2019-04-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR target/90178
+ Revert:
+ 2018-11-21 Uros Bizjak <ubizjak@gmail.com>
+
+ Revert the revert:
+ 2013-10-26 Vladimir Makarov <vmakarov@redhat.com>
+
+ Revert:
+ 2013-10-25 Vladimir Makarov <vmakarov@redhat.com>
+
+ * lra-spills.c (lra_final_code_change): Remove useless move insns.
+
2019-04-21 Iain Sandoe <iain@sandoe.co.uk>
* config/rs6000/rs6000.md (group_end_nop): Emit insn register
diff --git a/gcc/lra-spills.c b/gcc/lra-spills.c
index c19b76a579c..18db79e70a0 100644
--- a/gcc/lra-spills.c
+++ b/gcc/lra-spills.c
@@ -740,7 +740,6 @@ lra_final_code_change (void)
int i, hard_regno;
basic_block bb;
rtx_insn *insn, *curr;
- rtx set;
int max_regno = max_reg_num ();
for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
@@ -819,19 +818,5 @@ lra_final_code_change (void)
}
if (insn_change_p)
lra_update_operator_dups (id);
-
- if ((set = single_set (insn)) != NULL
- && REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
- && REGNO (SET_SRC (set)) == REGNO (SET_DEST (set)))
- {
- /* Remove an useless move insn. IRA can generate move
- insns involving pseudos. It is better remove them
- earlier to speed up compiler a bit. It is also
- better to do it here as they might not pass final RTL
- check in LRA, (e.g. insn moving a control register
- into itself). */
- lra_invalidate_insn_data (insn);
- delete_insn (insn);
- }
}
}
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ee1281e6cab..983382492f0 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2019-04-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR target/90178
+ * gcc.target/i386/pr90178.c: New test.
+
2019-04-20 Sandra Loosemore <sandra@codesourcery.com>
* g++.dg/ipa/pr89009.C: Add dg-require-effective-target fpic.
diff --git a/gcc/testsuite/gcc.target/i386/pr90178.c b/gcc/testsuite/gcc.target/i386/pr90178.c
new file mode 100644
index 00000000000..1df36af0541
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr90178.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx -mvzeroupper" } */
+
+int*
+find_ptr (int* mem, int sz, int val)
+{
+ for (int i = 0; i < sz; i++)
+ if (mem[i] == val)
+ return &mem[i];
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times "xorl\[\\t \]*\\\%eax,\[\\t \]*%eax" 1 } } */
--
2.20.1
