Re: [PATCH] PR target/103069: Relax cmpxchg loop for x86 target

2021-11-15 Thread Hongyu Wang via Gcc-patches
; > +FUNC_ATOMIC (int64_t, or) > > +FUNC_ATOMIC (int64_t, xor) > > +FUNC_ATOMIC (int, and) > > +FUNC_ATOMIC (int, nand) > > +FUNC_ATOMIC (int, or) > > +FUNC_ATOMIC (int, xor) > > +FUNC_ATOMIC (short, and) > > +FUNC_ATOMIC (short, nand) > > +FUNC_AT

Re: [PATCH] PR target/103069: Relax cmpxchg loop for x86 target

2021-11-15 Thread Uros Bizjak via Gcc-patches
On Sat, Nov 13, 2021 at 3:34 AM Hongyu Wang wrote: > > Hi, > > From the CPU's point of view, getting a cache line for writing is more > expensive than reading. See Appendix A.2 Spinlock in: > > https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/ >

[PATCH] PR target/103069: Relax cmpxchg loop for x86 target

2021-11-12 Thread Hongyu Wang via Gcc-patches
Hi, >From the CPU's point of view, getting a cache line for writing is more expensive than reading. See Appendix A.2 Spinlock in: https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/ xeon-lock-scaling-analysis-paper.pdf The full compare and swap will grab the cache line