ject: Re: [PATCH] RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering
optmization
> +rtx ops[] = {operands[0], operands[1], operands[2], operands[3]};
> +riscv_vector::emit_vlmax_ternary_insn (code_for_pred_widen_mul_plus
> (, mode),
> +riscv_vector::RVV_WIDEN_TERNOP, ops);
> +rtx ops[] = {operands[0], operands[1], operands[2], operands[3]};
> +riscv_vector::emit_vlmax_ternary_insn (code_for_pred_widen_mul_plus
> (, mode),
> +riscv_vector::RVV_WIDEN_TERNOP, ops);
ops is still there ;) No need for another revision thou
currently.
You can take a look at ARM SVE. There are also many combine "unspecs" patterns.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-06 19:42
To: 钟居哲; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; palmer; palmer; Jeff Law; pan2.li
Subject: Re: [PATCH] RISC-V: Add RVV v
> These enhance patterns are generated in complicate combining situations.
Yes, that's clear. One strategy is to look through combine's output and
see which combination results make sense for a particular backend.
I was wondering where the unspec-less patterns originate (when we
expand everything
.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-06 19:16
To: juzhe.zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; pan2.li
Subject: Re: [PATCH] RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering
optmization
Hi Juzhe,
just one/two really minor nits.
Hi Juzhe,
just one/two really minor nits.
> +rtx ops[] = {operands[0], operands[1], operands[2], operands[3]};
> +riscv_vector::emit_vlmax_ternary_insn (code_for_pred_widen_mul_plus
> (, mode),
> +riscv_vector::RVV_WIDEN_TERNOP, ops);
Here and in
From: Juzhe-Zhong
This patch add combine optimization for following case:
__attribute__ ((noipa)) void
vwmaccsu (int16_t *__restrict dst, int8_t *__restrict a, uint8_t *__restrict b,
int n)
{
for (int i = 0; i < n; i++)
dst[i] += (int16_t) a[i] * (int16_t) b[i];
}
Before this pat
