Sure thing, let me update it ASAP.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, April 14, 2023 10:35 AM
To: Li, Pan2 ; gcc-patches
Cc: Kito.cheng ; Wang, Yanzhang
; Li, Pan2
Subject: Re: [PATCH] RISC-V: Add test cases for the RVV mask insn shortcut.
+/* { dg-final { scan-assembler
\s+v[0-9]+,\s*v[0-9]+} } } */
It's better add more assembler check
check how many vmclr.m or vmset.m should be.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-04-14 10:32
To: gcc-patches
CC: juzhe.zhong; kito.cheng; yanzhang.wang; pan2.li
Subject: [PATCH] RISC-V: Add test cases for the RVV mask
From: Pan Li
There are sorts of shortcut codegen for the RVV mask insn. For
example.
vmxor vd, va, va => vmclr vd.
We would like to add more optimization like this but first of all
we must add the tests for the existing shortcut optimization, to
ensure we don't break existing optimization from
