Re: [PATCH] RISC-V: Add the Zihpm and Zicntr extensions

2024-01-19 Thread Kito Cheng
I realized we missed this on trunk, and I need this on adding -mcpu for sfive cores, so I'm gonna push this to trunk. Most concerns are around the assembler stuff, so I believe it's less controversial on the toolchain driver side. On Wed, Nov 23, 2022 at 6:01 AM Palmer Dabbelt wrote: > > On Tue,

Re: [PATCH] RISC-V: Add the Zihpm and Zicntr extensions

2022-11-22 Thread Palmer Dabbelt
On Tue, 22 Nov 2022 13:50:28 PST (-0800), jeffreya...@gmail.com wrote: On 11/22/22 08:29, Palmer Dabbelt wrote: On Tue, 22 Nov 2022 07:20:15 PST (-0800), jeffreya...@gmail.com wrote: On 11/20/22 18:36, Kito Cheng wrote: So the idea here is just to define the extension so that it gets

Re: [PATCH] RISC-V: Add the Zihpm and Zicntr extensions

2022-11-22 Thread Jeff Law via Gcc-patches
On 11/22/22 08:29, Palmer Dabbelt wrote: On Tue, 22 Nov 2022 07:20:15 PST (-0800), jeffreya...@gmail.com wrote: On 11/20/22 18:36, Kito Cheng wrote: So the idea here is just to define the extension so that it gets defined in the ISA strings and passed through to the assembler, right? That

Re: [PATCH] RISC-V: Add the Zihpm and Zicntr extensions

2022-11-22 Thread Palmer Dabbelt
On Tue, 22 Nov 2022 07:20:15 PST (-0800), jeffreya...@gmail.com wrote: On 11/20/22 18:36, Kito Cheng wrote: So the idea here is just to define the extension so that it gets defined in the ISA strings and passed through to the assembler, right? That will also define arch test marco:

Re: [PATCH] RISC-V: Add the Zihpm and Zicntr extensions

2022-11-22 Thread Jeff Law via Gcc-patches
On 11/20/22 18:36, Kito Cheng wrote: So the idea here is just to define the extension so that it gets defined in the ISA strings and passed through to the assembler, right? That will also define arch test marco:

Re: [PATCH] RISC-V: Add the Zihpm and Zicntr extensions

2022-11-20 Thread Kito Cheng via Gcc-patches
> So the idea here is just to define the extension so that it gets defined > in the ISA strings and passed through to the assembler, right? That will also define arch test marco: https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md#architecture-extension-test-macro On

Re: [PATCH] RISC-V: Add the Zihpm and Zicntr extensions

2022-11-20 Thread Jeff Law via Gcc-patches
On 11/8/22 20:00, Palmer Dabbelt wrote: These extensions were recently frozen [1]. As per Andrew's post [2] we're meant to ignore these in software, this just adds them to the list of allowed extensions and otherwise ignores them. I added these under SPEC_CLASS_NONE even though the PDF lists

Re: [PATCH] RISC-V: Add the Zihpm and Zicntr extensions

2022-11-17 Thread Palmer Dabbelt
On Thu, 17 Nov 2022 18:14:18 PST (-0800), christoph.muell...@vrull.eu wrote: On Wed, Nov 9, 2022 at 4:01 AM Palmer Dabbelt wrote: These extensions were recently frozen [1]. As per Andrew's post [2] we're meant to ignore these in software, this just adds them to the list of allowed extensions

Re: [PATCH] RISC-V: Add the Zihpm and Zicntr extensions

2022-11-17 Thread Christoph Müllner
On Wed, Nov 9, 2022 at 4:01 AM Palmer Dabbelt wrote: > These extensions were recently frozen [1]. As per Andrew's post [2] > we're meant to ignore these in software, this just adds them to the list > of allowed extensions and otherwise ignores them. I added these under > SPEC_CLASS_NONE even

[PATCH] RISC-V: Add the Zihpm and Zicntr extensions

2022-11-08 Thread Palmer Dabbelt
These extensions were recently frozen [1]. As per Andrew's post [2] we're meant to ignore these in software, this just adds them to the list of allowed extensions and otherwise ignores them. I added these under SPEC_CLASS_NONE even though the PDF lists them as 20190614 because it seems pointless