Merged two changes into one patch, and committed to master :)
On Mon, Oct 24, 2022 at 10:28 AM wrote:
>
> From: Ju-Zhe Zhong
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_legitimize_move): Adjust using
> force_reg.
>
> ---
> gcc/config/riscv/riscv.cc | 4 +---
> 1 file changed,
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_move): Adjust using force_reg.
---
gcc/config/riscv/riscv.cc | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 98374a922d1..1fd34
Address comments. Fix it soon.
juzhe.zh...@rivai.ai
From: Andrew Pinski
Date: 2022-10-24 10:14
To: juzhe.zhong
CC: gcc-patches; kito.cheng
Subject: Re: [PATCH] RISC-V: Support (set (mem) (const_poly_int))
On Sun, Oct 23, 2022 at 7:04 PM wrote:
>
> From: Ju-Zhe Zhong
>
> g
On Sun, Oct 23, 2022 at 7:04 PM wrote:
>
> From: Ju-Zhe Zhong
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem)
> (const_poly_int)).
>
> ---
> gcc/config/riscv/riscv.cc | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/gcc/
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem)
(const_poly_int)).
---
gcc/config/riscv/riscv.cc | 14 ++
1 file changed, 14 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 90a390
I made a mistake in this patch. I mixed 2 commits into a single patch.
Sorry about that. Please ignore this patch. Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2022-10-24 09:53
To: gcc-patches
CC: kito.cheng; palmer; Ju-Zhe Zhong
Subject: [PATCH] RISC-V: Support (set (mem
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vector-switch.def (ENTRY): Remove TI/TF.
* config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem)
(const_poly_int)).
---
gcc/config/riscv/riscv-vector-switch.def | 4
gcc/config/riscv/riscv.cc
