Thanks, I will push a V2 patch, to fix the typo and add a vector cost model
for p600 series.
About block the div units, I decided to use your suggestion. The P600
series
divider is 4 bits per cycle. So blocking 3-5 cycles is enough.
On Thu, Feb 1, 2024 at 9:50 AM Edwin Lu wrote:
> I recently c
I recently committed changes modifying the scheduling reservations. Some
things may need to be retested with the newly enabled asserts.
Edwin
On 1/31/2024 1:40 AM, Monk Chiang wrote:
Add sifive p600 series scheduler module. For more information
see https://www.sifive.com/cores/performance-p650
> + NULL, /* vector cost */
> +};
Does the P600 series include a vector unit? From what I found on
the web it looks like it. If so I would suggest specifying at least
the default (generic) vector cost model here. We fall back to the
default one for
Add sifive p600 series scheduler module. For more information
see https://www.sifive.com/cores/performance-p650-670.
Add sifive-p650, sifive-p670 for mcpu option will come in separate patches.
gcc/ChangeLog:
* config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
attribute, and in
