From: Juzhe-Zhong
This patch is to add WHILE_LEN pattern.
It's inspired by RVV ISA simple "vvaddint32.s" example:
https://github.com/riscv/riscv-v-spec/blob/master/example/vvaddint32.s
More details are in "vect_set_loop_controls_by_while_len" implementation
and comments.
Consider such following
: richard.sandif...@arm.com; rguent...@suse.de; jeffreya...@gmail.com;
Juzhe-Zhong
Subject: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for
auto-vectorization
From: Juzhe-Zhong
This patch is to add WHILE_LEN pattern.
It's inspired by RVV ISA simple "vvaddint32.s" example:
htt
; jeffreyalaw; Juzhe-Zhong
Subject: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for
auto-vectorization
From: Juzhe-Zhong
This patch is to add WHILE_LEN pattern.
It's inspired by RVV ISA simple "vvaddint32.s" example:
https://github.com/riscv/riscv-v-spec/blob/master/examp
; jeffreyalaw; Juzhe-Zhong
> Subject: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for
> auto-vectorization
> From: Juzhe-Zhong
>
> This patch is to add WHILE_LEN pattern.
> It's inspired by RVV ISA simple "vvaddint32.s" example:
09:47
> > To: gcc-patches
> > CC: richard.sandiford; rguenther; jeffreyalaw; Juzhe-Zhong
> > Subject: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for
> > auto-vectorization
> > From: Juzhe-Zhong
> >
> > This patch is to add WHILE_LEN p
>> I think we can CC IBM folks to see whether we can make WHILE_LEN works
>> for both IBM and RVV ?
>
> I've CCed them. Adding WHILE_LEN support to rs6000/s390x would be
> mainly the "easy" way to get len-masked (epilog) loop support. I've
> figured actually implementing WHILE_ULT for AVX512 in
Richard Biener writes:
> On Wed, 12 Apr 2023, juzhe.zh...@rivai.ai wrote:
>
>>
>> >> Thanks for the detailed explanation. Just to clarify - with RVV
>> >> there's only a single mask register, v0.t, or did you want to
>> >> say an instruction can only specify a single mask register?
>>
>> RVV ha
On Wed, Apr 12, 2023 at 1:18 PM Richard Sandiford via Gcc-patches
wrote:
>
> Richard Biener writes:
> > On Wed, 12 Apr 2023, juzhe.zh...@rivai.ai wrote:
> >
> >>
> >> >> Thanks for the detailed explanation. Just to clarify - with RVV
> >> >> there's only a single mask register, v0.t, or did you
"juzhe.zh...@rivai.ai" writes:
>>> I think that already works for them (could be misremembering).
>>> However, IIUC, they have no special instruction to calculate the
>>> length (unlike for RVV), and so it's open-coded using vect_get_len.
>
> Yeah, the current flow using min, sub, and then min in
Hi!
on 2023/4/12 19:37, juzhe.zh...@rivai.ai wrote:
> Thank you. Richard. >> I think that already works for them (could be
> misremembering). >> However, IIUC, they have no special instruction to
> calculate the >> length (unlike for RVV), and so it's open-coded using
> vect_get_len.
>
> Than
Hi Juzhe,
on 2023/4/12 21:22, 钟居哲 wrote:
> Thanks Kewen.
>
> It seems that this proposal WHILE_LEN can help s390 when using --param
> vect-partial-vector-usage=2 compile option.
>
Yeah, IMHO, the previous sequence vs. the proposed sequence are like:
int
foo (int *__restrict a, int *__restric
Hi Juzhe,
on 2023/4/13 21:44, 钟居哲 wrote:
> Thanks Kewen.
>
> Current flow in this patch like you said:
>
> len = WHILE_LEN (n,vf);
> ...
> v = len_load (addr,len);
> ..
> addr = addr + vf (in byte align);
>
>
> This patch is just keep adding address with a vector factor (adjust as byte
Hi Juzhe,
>>> Yes, we just wants to add the whole vector register length in bytes.
> OK, I learn it and appreciate you give me the information.
>
>>> I wonder if you also want WHILE_LEN to have the implicit effect
>>>to update vector length register?
>>>From this perspective, Richi's
>>>suggestio
Hi Juzhe,
on 2023/4/14 11:39, juzhe.zh...@rivai.ai wrote:
> And also I already decided to make remove WHILE_LEN pattern since it seems to
> be unnecessary.
> And as Richard said, it's just a simple airthmetic and it's not worthwhile to
> do that.
> > So, I plan to replace WHILE_LEN into MIN_EXPR
on 2023/4/14 14:39, juzhe.zh...@rivai.ai wrote:
>>> Yeah, MIN_EXPR is enough for IBM ports, but with seeing the special
>>> semantic of vsetvli on
>>> "vl = ceil(AVL / 2) for VLMAX < AVL < 2*VLMAX", I'm not sure if it's a good
>>>idea for RV, it seems
>>> to put the burden to RV backend. For one
"juzhe.zh...@rivai.ai" writes:
>>> But the issue is the same in the reverse with WHILE_LEN, no?
>>>WHILE_LEN just computes a scalar value - you seem to suggest
>>>there's a hidden side-effect of "coalescing" the result with
>>>a hardware vector length register? I don't think that's good design.
>
he-Zhong
Subject: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for
auto-vectorization
From: Juzhe-Zhong
This patch is to add WHILE_LEN pattern.
It's inspired by RVV ISA simple "vvaddint32.s" example:
https://github.com/riscv/riscv-v-spec/blob/master/example/vvaddint32.
g
> Date: 2023-04-07 09:47
> To: gcc-patches
> CC: richard.sandiford; rguenther; jeffreyalaw; Juzhe-Zhong
> Subject: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for
> auto-vectorization
> From: Juzhe-Zhong
>
> This patch is to add WHILE_LEN pattern.
>
given that even
> non-final iterations might process fewer than VF elements.
>
> Thanks,
> Richard
>
>> juzhe.zh...@rivai.ai
>>
>> From: juzhe.zhong
>> Date: 2023-04-07 09:47
>> To: gcc-patches
>> CC: richard.sandiford; rguenther; jeffr
"juzhe.zh...@rivai.ai" writes:
> OK. Thanks Richard.
> So let me conclude:
> 1. Community agree that I should support variable IV in the middle-end.
> 2. We can keep WHILE_LEN pattern when "not only final iteration is partial".
> And I should describe it more clearly in the doc.
>
> I should d
On Thu, 20 Apr 2023, Richard Sandiford wrote:
> "juzhe.zh...@rivai.ai" writes:
> > OK. Thanks Richard.
> > So let me conclude:
> > 1. Community agree that I should support variable IV in the middle-end.
> > 2. We can keep WHILE_LEN pattern when "not only final iteration is partial".
> > And I
Richard Biener writes:
> On Thu, 20 Apr 2023, Richard Sandiford wrote:
>
>> "juzhe.zh...@rivai.ai" writes:
>> > OK. Thanks Richard.
>> > So let me conclude:
>> > 1. Community agree that I should support variable IV in the middle-end.
>> > 2. We can keep WHILE_LEN pattern when "not only final iter
to comment if you have any questions.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-04-12 15:00
To: Richard Sandiford
CC: juzhe.zh...@rivai.ai; gcc-patches; jeffreyalaw
Subject: Re: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for
auto-vectorization
On Tue, 11
ctions.
For AVX512 WHILE_ULT is a better match since we need a mask in the
end (but WHILE_ULT isn't a very good match either, so I'm still
working on masked loop support there).
PowerPC and s390x might be able to use WHILE_LEN as well (though
they only have LEN variants of loads and s
nerated
by comparison)
I think we can CC IBM folks to see whether we can make WHILE_LEN works
for both IBM and RVV ?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-04-12 16:42
To: juzhe.zh...@rivai.ai
CC: richard.sandiford; gcc-patches; jeffreyalaw
Subject: Re: Re: [PATCH] V
for the if (cond[i]) which would be combined with a mask-and
instruction to a third mask which is then used on the
predicated instructions.
For AVX512 WHILE_ULT is a better match since we need a mask in the
end (but WHILE_ULT isn't a very good match either, so I'm still
workin
ed actually implementing WHILE_ULT for AVX512 in the backend
results in some code generation challenges so I'm going to play
(again) with open-coding it as outlined above in the vectorizer itself
so followup passes (mostly IVOPTs) can do a better job.
Richard.
>
> Thanks.
>
>
related
addressing-mode choosing.
I think I must missed something, would you mind giving me some hints so that I
can study on ivopts
to find out which case may generate inferior codegens for varialble IV step?
Thank you so much.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-04-12 19:17
rivai.ai; richard.sandiford; rguenther
CC: gcc-patches; jeffreyalaw; rdapp
Subject: Re: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for
auto-vectorization
Hi!
on 2023/4/12 19:37, juzhe.zh...@rivai.ai wrote:
> Thank you. Richard. >> I think that already works f
ai.ai
CC: rguenther; gcc-patches; jeffreyalaw; rdapp; linkw
Subject: Re: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for
auto-vectorization
"juzhe.zh...@rivai.ai" writes:
>>> I think that already works for them (could be misremembering).
>>> However
LE_LEN is that it is a key
for the vectorizer to query target capabilities (and preferences).
But of course collecting whether stmts can be vectorized
with length and/or with mask would be better.
Richard.
> CC RISC-V port backend maintainer: Kito.
>
>
>
> juzhe.zh...@rivai.ai
>
V hardware and the open-source
simulator generate "vl" = VLMAX. (Sorry about that)
Expecting any suggestions and comments.
Thank you so much.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-04-13 14:47
To: 钟居哲
CC: richard.sandiford; gcc-patches; Jeff Law; rdapp; linkw; kito.chen
o hardward loop optimization when IV loop control is
variable ?
juzhe.zh...@rivai.ai
From: Kewen.Lin
Date: 2023-04-13 15:29
To: 钟居哲
CC: gcc-patches; Jeff Law; rdapp; richard.sandiford; rguenther
Subject: Re: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for
auto-vectorization
Hi
i.ai
From: Kewen.Lin
Date: 2023-04-14 10:54
To: 钟居哲
CC: gcc-patches; Jeff Law; rdapp; richard.sandiford; rguenther
Subject: Re: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for
auto-vectorization
Hi Juzhe,
on 2023/4/13 21:44, 钟居哲 wrote:
> Thanks Kewen.
>
> Current f
hat we can switch to this flow ?
Is it more reasonable ?
Thanks.
juzhe.zh...@rivai.ai
From: Kewen.Lin
Date: 2023-04-14 10:54
To: 钟居哲
CC: gcc-patches; Jeff Law; rdapp; richard.sandiford; rguenther
Subject: Re: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for
auto-vectorization
Hi Ju
backend patches on vector with length
>> exploitation since
>> the existing vector with length support already works well on functionality.
Ok, I get your point. I am gonna refine the patch to make it work for both RVV
and IBM.
Thanks all your comments.
juzhe.zh...@rivai.ai
; To: ???
> CC: gcc-patches; Jeff Law; rdapp; richard.sandiford; rguenther
> Subject: Re: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for
> auto-vectorization
> Hi Juzhe,
>
> on 2023/4/13 21:44, ??? wrote:
> > Thanks Kewen.
> >
> > Current flow in
Sandiford
Date: 2023-04-20 16:52
To: 钟居哲
CC: gcc-patches; rguenther; Jeff Law
Subject: Re: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for
auto-vectorization
钟居哲 writes:
> Hi, Richards.
> Since GCC 14 is open and this patch has been boostraped && tested on X86.
&
date patch.
Is that right? Feel free to correct me.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-04-20 17:11
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther; jeffreyalaw
Subject: Re: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for
auto-vectorization
function.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-04-20 17:54
To: Richard Biener
CC: juzhe.zhong\@rivai.ai; gcc-patches; jeffreyalaw
Subject: Re: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for
auto-vectorization
Richard Biener writes:
> On Thu, 20 Apr 20
patches; jeffreyalaw
> Subject: Re: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for
> auto-vectorization
> Richard Biener writes:
> > On Thu, 20 Apr 2023, Richard Sandiford wrote:
> >
> >> "juzhe.zh...@rivai.ai" writes:
> >> >
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