ivai.ai
CC: gcc-patches; rguenther; kito.cheng
Subject: Re: [PATCH] middle-end: skipp stepped vector test of poly_int (1, 1)
and allow the machine_mode definition with poly_uint16 (1, 1)
"juzhe.zh...@rivai.ai" writes:
> Thanks for your reply. Your suggestion "-1 - (int) i" i
roblematic
>> for (1,1) then an interleaving of 2 stepped vectors (i.e. npatterns==2)
>> would be problematic for (2,2).
>>
>> So yeah, preventing a mode being used for autovectorisation would allow
>> the target to have a bit more control over which constants are ac
it yourself?
Thank you so much.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2022-08-22 16:31
To: 钟居哲
CC: rguenther; gcc-patches; kito.cheng
Subject: Re: [PATCH] middle-end: skipp stepped vector test of poly_int (1, 1)
and allow the machine_mode definition with poly_uint16 (1, 1)
hink only allow poly (1,1)mode used in intrinsics
>> will
>> not create issues. Am I understanding wrong ？Feel free to correct me. Thanks
>> ~
>
> Following on from what I said above, it doesn't look like this particular
> case is related to stepped vect
ts are actually
generated. But it shouldn't be necessary to do that for correctness.
Thanks,
Richard
> juzhe.zh...@rivai.ai
>
> From: Richard Sandiford
> Date: 2022-08-19 17:35
> To: juzhe.zhong\@rivai.ai
> CC: rguenther; gcc-patches; kito.cheng
> Subjec
n ?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2022-08-19 20:52
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther; kito.cheng
Subject: Re: [PATCH] middle-end: skipp stepped vector test of poly_int (1, 1)
and allow the machine_mode definition with poly_uint16 (1, 1)
"ju
; Finally, I tried:
>> if (!nunits.is_constant () && known_gt (GET_MODE_NUNITS (inner_mode), 1))
>> test_vector_subregs_modes (x, nunits - min_nunits, count);
>> It passed with no warning.
>>
>> Is 'known_gt (GET_MODE_NUNITS (inner_mode), 1)' a good so
stant () && known_gt (GET_MODE_NUNITS (inner_mode), 1))
>> test_vector_subregs_modes (x, nunits - min_nunits, count);
>> It passed with no warning.
>>
>> Is 'known_gt (GET_MODE_NUNITS (inner_mode), 1)' a good solution for this?
>> Thanks!
>>
ode), 1)' a good solution for this?
> Thanks!
>
>
> juzhe.zh...@rivai.ai
>
> From: Richard Sandiford
> Date: 2022-08-19 16:03
> To: juzhe.zhong
> CC: gcc-patches; rguenther; kito.cheng
> Subject: Re: [PATCH] middle-end: skipp stepped vector test of poly_int (1, 1)
gt; Date: 2022-08-19 16:03
> To: juzhe.zhong
> CC: gcc-patches; rguenther; kito.cheng
> Subject: Re: [PATCH] middle-end: skipp stepped vector test of poly_int (1, 1)
> and allow the machine_mode definition with poly_uint16 (1, 1)
> juzhe.zh...@rivai.ai writes:
>> From: zhongjuzh
c-patches; rguenther; kito.cheng
Subject: Re: [PATCH] middle-end: skipp stepped vector test of poly_int (1, 1)
and allow the machine_mode definition with poly_uint16 (1, 1)
juzhe.zh...@rivai.ai writes:
> From: zhongjuzhe
>
> Hello. This patch is preparing for following RVV support.
>
>
CH] middle-end: skipp stepped vector test of poly_int (1, 1)
and allow the machine_mode definition with poly_uint16 (1, 1)
juzhe.zh...@rivai.ai writes:
> From: zhongjuzhe
>
> Hello. This patch is preparing for following RVV support.
>
> Both ARM SVE and RVV (RISC-V 'V'
juzhe.zh...@rivai.ai writes:
> From: zhongjuzhe
>
> Hello. This patch is preparing for following RVV support.
>
> Both ARM SVE and RVV (RISC-V 'V' Extension) support length-agnostic vector.
> The minimum vector length of ARM SVE is 128-bit and the runtime invariant of
> ARM SVE is always 128-bit
From: zhongjuzhe
Hello. This patch is preparing for following RVV support.
Both ARM SVE and RVV (RISC-V 'V' Extension) support length-agnostic vector.
The minimum vector length of ARM SVE is 128-bit and the runtime invariant of
ARM SVE is always 128-bit blocks.
However, the minimum vector lengt
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