[PATCH] recog: Fix a constrain_operands corner case [PR97144]

aarch64's *add3_poly_1 has a pattern with the constraints: "=...,r,&r" "...,0,rk" "...,Uai,Uat" i.e. the penultimate alternative requires operands 0 and 1 to match, but the final alternative does not allow them to match. The register allocators dealt with this correctly, and so used differ

Re: [PATCH] recog: Fix a constrain_operands corner case [PR97144]

On Thu, Dec 31, 2020 at 7:57 AM Richard Sandiford via Gcc-patches wrote: > > aarch64's *add3_poly_1 has a pattern with the constraints: > > "=...,r,&r" > "...,0,rk" > "...,Uai,Uat" > > i.e. the penultimate alternative requires operands 0 and 1 to match, > but the final alternative does not a

Re: [PATCH] recog: Fix a constrain_operands corner case [PR97144]

"H.J. Lu" writes: > On Thu, Dec 31, 2020 at 7:57 AM Richard Sandiford via Gcc-patches > wrote: >> >> aarch64's *add3_poly_1 has a pattern with the constraints: >> >> "=...,r,&r" >> "...,0,rk" >> "...,Uai,Uat" >> >> i.e. the penultimate alternative requires operands 0 and 1 to match, >> but

Re: [PATCH] recog: Fix a constrain_operands corner case [PR97144]

On Thu, Dec 31, 2020 at 8:21 AM Richard Sandiford wrote: > > "H.J. Lu" writes: > > On Thu, Dec 31, 2020 at 7:57 AM Richard Sandiford via Gcc-patches > > wrote: > >> > >> aarch64's *add3_poly_1 has a pattern with the constraints: > >> > >> "=...,r,&r" > >> "...,0,rk" > >> "...,Uai,Uat" > >>