On Tue, Sep 15, 2020 at 10:48:37AM -0500, Peter Bergner wrote:
> > rs6000_is_valid_shift_mask handles this already (but it requires you to
> > pass in the shift needed). rs6000_is_valid_mask will handle it.
> > rs6000_is_valid_and_mask does not get a shift count parameter, so cannot
> > use rldic
> rs6000_is_valid_shift_mask handles this already (but it requires you to
> pass in the shift needed). rs6000_is_valid_mask will handle it.
> rs6000_is_valid_and_mask does not get a shift count parameter, so cannot
> use rldic currently.
After talking with you off line, I changed to using rs6000_
Hi!
On Tue, Sep 15, 2020 at 02:23:16PM +0930, Alan Modra wrote:
> On Thu, Sep 10, 2020 at 04:58:03PM -0500, Peter Bergner via Gcc-patches wrote:
> > +unsigned long
> > +test0 (void)
> > +{
> > + return 0x0000UL;
> > +}
> > +
> > +unsigned long
> > +test1 (void)
> > +{
> > + return
Hi!
On Thu, Sep 10, 2020 at 04:58:03PM -0500, Peter Bergner wrote:
> Generating arbitrary 64-bit constants on POWER can take up to 5 instructions.
> However, some special constants can be generated in fewer instructions.
> One special class of constants we don't handle, is constants that have one
On Thu, Sep 10, 2020 at 04:58:03PM -0500, Peter Bergner via Gcc-patches wrote:
> +unsigned long
> +test0 (void)
> +{
> + return 0x0000UL;
> +}
> +
> +unsigned long
> +test1 (void)
> +{
> + return 0x0000UL;
> +}
> +
> +unsigned long
> +test2 (void)
> +{
> + return 0x00f
Generating arbitrary 64-bit constants on POWER can take up to 5 instructions.
However, some special constants can be generated in fewer instructions.
One special class of constants we don't handle, is constants that have one
set of consecutive 1-bits. These can be generated with a "li rT,-1"
follo
