Re: [PATCH] rtlanal: Fix nonzero_bits for non-load paradoxical subregs (PR85925)

2018-09-18 Thread Eric Botcazou
> Do you have any progress with this? Once I'm done with the recent regressions, I'll get back to this older one. -- Eric Botcazou

Re: [PATCH] rtlanal: Fix nonzero_bits for non-load paradoxical subregs (PR85925)

2018-09-17 Thread Segher Boessenkool
On Mon, Jun 04, 2018 at 10:57:05PM +0200, Eric Botcazou wrote: > > In the PR we have insns: > > > > Trying 23 -> 24: > >23: r123:SI=zero_extend(r122:HI) > > REG_DEAD r122:HI > >24: [r115:SI]=r123:SI > > REG_DEAD r123:SI > > > > which should be combined to > > > > (set (mem:SI

Re: [PATCH] rtlanal: Fix nonzero_bits for non-load paradoxical subregs (PR85925)

2018-06-04 Thread Eric Botcazou
> I can see why WORD_REGISTER_OPERATIONS allows some REG cases, > but why does LOAD_EXTEND_OP have an effect on them? LOAD_EXTEND_OP has an effect on all paradoxical SUBREGs because of spilling. This was even originally decoupled from WORD_REGISTER_OPERATIONS in reload, see this comment from fi

Re: [PATCH] rtlanal: Fix nonzero_bits for non-load paradoxical subregs (PR85925)

2018-06-04 Thread Richard Sandiford
Eric Botcazou writes: >> In the PR we have insns: >> >> Trying 23 -> 24: >>23: r123:SI=zero_extend(r122:HI) >> REG_DEAD r122:HI >>24: [r115:SI]=r123:SI >> REG_DEAD r123:SI >> >> which should be combined to >> >> (set (mem:SI (reg/f:SI 115 [ pretmp_19 ]) [1 *pretmp_19+0 S4 A3

Re: [PATCH] rtlanal: Fix nonzero_bits for non-load paradoxical subregs (PR85925)

2018-06-04 Thread Eric Botcazou
> In the PR we have insns: > > Trying 23 -> 24: >23: r123:SI=zero_extend(r122:HI) > REG_DEAD r122:HI >24: [r115:SI]=r123:SI > REG_DEAD r123:SI > > which should be combined to > > (set (mem:SI (reg/f:SI 115 [ pretmp_19 ]) [1 *pretmp_19+0 S4 A32]) > (and:SI (subreg:SI (reg:

[PATCH] rtlanal: Fix nonzero_bits for non-load paradoxical subregs (PR85925)

2018-06-04 Thread Segher Boessenkool
Hi! In the PR we have insns: Trying 23 -> 24: 23: r123:SI=zero_extend(r122:HI) REG_DEAD r122:HI 24: [r115:SI]=r123:SI REG_DEAD r123:SI which should be combined to (set (mem:SI (reg/f:SI 115 [ pretmp_19 ]) [1 *pretmp_19+0 S4 A32]) (and:SI (subreg:SI (reg:HI 122) 0)