On Wed, Jul 28, 2021 at 5:00 AM Hongtao Liu via Gcc-patches
wrote:
>
> On Wed, Jul 28, 2021 at 10:46 AM H.J. Lu wrote:
> >
> > On Tue, Jul 27, 2021 at 7:02 PM Hongtao Liu wrote:
> > >
> > > On Tue, Jul 27, 2021 at 10:46 PM H.J. Lu via Gcc-patches
> > > wrote:
> > > >
> > > > There is no SSE <->
On Wed, Jul 28, 2021 at 10:46 AM H.J. Lu wrote:
>
> On Tue, Jul 27, 2021 at 7:02 PM Hongtao Liu wrote:
> >
> > On Tue, Jul 27, 2021 at 10:46 PM H.J. Lu via Gcc-patches
> > wrote:
> > >
> > > There is no SSE <-> AVX transition penalty if the upper bits of YMM/ZMM
> > > registers are unchanged and
On Tue, Jul 27, 2021 at 7:02 PM Hongtao Liu wrote:
>
> On Tue, Jul 27, 2021 at 10:46 PM H.J. Lu via Gcc-patches
> wrote:
> >
> > There is no SSE <-> AVX transition penalty if the upper bits of YMM/ZMM
> > registers are unchanged and YMM/ZMM store doesn't change the upper bits
> > of YMM/ZMM regis
On Tue, Jul 27, 2021 at 10:46 PM H.J. Lu via Gcc-patches
wrote:
>
> There is no SSE <-> AVX transition penalty if the upper bits of YMM/ZMM
> registers are unchanged and YMM/ZMM store doesn't change the upper bits
> of YMM/ZMM registers.
>
> 1. Since zeroing YMM/ZMM register is implemented with ze
There is no SSE <-> AVX transition penalty if the upper bits of YMM/ZMM
registers are unchanged and YMM/ZMM store doesn't change the upper bits
of YMM/ZMM registers.
1. Since zeroing YMM/ZMM register is implemented with zeroing XMM
register, don't set AVX_U128_DIRTY when zeroing YMM/ZMM register.
