On 9/4/25 8:28 AM, Paul-Antoine Arras wrote:
This is a slightly amended patch that fixes modes and instruction type
attribute. Here is the relevant snippet:
diff --git gcc/config/riscv/autovec-opt.md gcc/config/riscv/autovec-opt.md
index d4335dc04ba..67f4d9ce3a8 100644
--- gcc/config/riscv/a
This is a slightly amended patch that fixes modes and instruction type
attribute. Here is the relevant snippet:
diff --git gcc/config/riscv/autovec-opt.md gcc/config/riscv/autovec-opt.md
index d4335dc04ba..67f4d9ce3a8 100644
--- gcc/config/riscv/autovec-opt.md
+++ gcc/config/riscv/autovec-opt.md
This pattern enables the combine pass (or late-combine, depending on the case)
to merge a float_extend'ed vec_duplicate into a mult RTL instruction.
Before this patch, we have six instructions, e.g.:
fcvt.d.sfa0,fa0
vsetvli a5,zero,e64,m1,ta,ma
vfmv.v.fv3,fa0
vfwcvt
