On Fri, Sep 23, 2022 at 2:26 AM Tamar Christina via Gcc-patches
wrote:
>
> Hi All,
>
> This is an RFC to figure out how to deal with targets that don't have native
> comparisons against QImode values.
>
> Booleans, at least in C99 and higher are 0-1 valued. This means that we only
> really need
> Am 30.09.2022 um 16:29 schrieb Richard Sandiford via Gcc-patches
> :
>
> Tamar Christina writes:
>>> -Original Message-
>>> From: Richard Biener
>>> Sent: Friday, September 30, 2022 12:53 PM
>>> To: Tamar Christina
>>> Cc: Richard Sandiford ; Tamar Christina via
>>> Gcc-patches
Tamar Christina writes:
>> -Original Message-
>> From: Richard Biener
>> Sent: Friday, September 30, 2022 12:53 PM
>> To: Tamar Christina
>> Cc: Richard Sandiford ; Tamar Christina via
>> Gcc-patches ; nd ; Jeff Law
>>
>> Subject: RE: [PATCH 1/2]middle-end: RFC: On expansion of
> -Original Message-
> From: Richard Biener
> Sent: Friday, September 30, 2022 12:53 PM
> To: Tamar Christina
> Cc: Richard Sandiford ; Tamar Christina via
> Gcc-patches ; nd ; Jeff Law
>
> Subject: RE: [PATCH 1/2]middle-end: RFC: On expansion of conditional
> branches, give hint if
On Fri, 30 Sep 2022, Tamar Christina wrote:
> > -Original Message-
> > From: Richard Biener
> > Sent: Friday, September 30, 2022 11:17 AM
> > To: Tamar Christina
> > Cc: Richard Sandiford ; Tamar Christina via
> > Gcc-patches ; nd ; Jeff Law
> >
> > Subject: RE: [PATCH 1/2]middle-end:
> -Original Message-
> From: Richard Biener
> Sent: Friday, September 30, 2022 11:17 AM
> To: Tamar Christina
> Cc: Richard Sandiford ; Tamar Christina via
> Gcc-patches ; nd ; Jeff Law
>
> Subject: RE: [PATCH 1/2]middle-end: RFC: On expansion of conditional
> branches, give hint if
On Fri, 30 Sep 2022, Tamar Christina wrote:
>
>
> > -Original Message-
> > From: Richard Sandiford
> > Sent: Friday, September 30, 2022 9:49 AM
> > To: Tamar Christina
> > Cc: Richard Biener ; Tamar Christina via Gcc-patches
> > ; nd ; Jeff Law
> >
> > Subject: Re: [PATCH
> -Original Message-
> From: Richard Sandiford
> Sent: Friday, September 30, 2022 9:49 AM
> To: Tamar Christina
> Cc: Richard Biener ; Tamar Christina via Gcc-patches
> ; nd ; Jeff Law
>
> Subject: Re: [PATCH 1/2]middle-end: RFC: On expansion of conditional
> branches, give hint if
Tamar Christina writes:
>> -Original Message-
>> From: Richard Sandiford
>> Sent: Friday, September 30, 2022 9:29 AM
>> To: Tamar Christina
>> Cc: Richard Biener ; Tamar Christina via Gcc-patches
>> ; nd ; Jeff Law
>>
>> Subject: Re: [PATCH 1/2]middle-end: RFC: On expansion of
> -Original Message-
> From: Richard Sandiford
> Sent: Friday, September 30, 2022 9:29 AM
> To: Tamar Christina
> Cc: Richard Biener ; Tamar Christina via Gcc-patches
> ; nd ; Jeff Law
>
> Subject: Re: [PATCH 1/2]middle-end: RFC: On expansion of conditional
> branches, give hint if
Tamar Christina writes:
>> -Original Message-
>> From: Gcc-patches > bounces+tamar.christina=arm@gcc.gnu.org> On Behalf Of Richard
>> Biener via Gcc-patches
>> Sent: Thursday, September 29, 2022 12:09 PM
>> To: Tamar Christina via Gcc-patches
>> Cc: Richard Sandiford ; nd
>>
> -Original Message-
> From: Gcc-patches bounces+tamar.christina=arm@gcc.gnu.org> On Behalf Of Richard
> Biener via Gcc-patches
> Sent: Thursday, September 29, 2022 12:09 PM
> To: Tamar Christina via Gcc-patches
> Cc: Richard Sandiford ; nd
> Subject: Re: [PATCH 1/2]middle-end: RFC:
On 9/29/22 03:37, Richard Sandiford wrote:
Jeff Law writes:
On 9/28/22 09:04, Richard Sandiford wrote:
Tamar Christina writes:
Maybe the target could use (subreg:SI (reg:BI ...)) as argument. Heh.
But then I'd still need to change the expansion code. I suppose this could
prevent the
> Am 29.09.2022 um 12:23 schrieb Tamar Christina via Gcc-patches
> :
>
>
>>
>> -Original Message-
>> From: Richard Biener
>> Sent: Thursday, September 29, 2022 10:41 AM
>> To: Richard Sandiford
>> Cc: Jeff Law ; Tamar Christina
>> ; gcc-patches@gcc.gnu.org; nd
>> Subject: Re:
> -Original Message-
> From: Richard Biener
> Sent: Thursday, September 29, 2022 10:41 AM
> To: Richard Sandiford
> Cc: Jeff Law ; Tamar Christina
> ; gcc-patches@gcc.gnu.org; nd
> Subject: Re: [PATCH 1/2]middle-end: RFC: On expansion of conditional
> branches, give hint if argument is
On Thu, 29 Sep 2022, Richard Sandiford wrote:
> Jeff Law writes:
> > On 9/28/22 09:04, Richard Sandiford wrote:
> >> Tamar Christina writes:
> Maybe the target could use (subreg:SI (reg:BI ...)) as argument. Heh.
> >>> But then I'd still need to change the expansion code. I suppose this
Jeff Law writes:
> On 9/28/22 09:04, Richard Sandiford wrote:
>> Tamar Christina writes:
Maybe the target could use (subreg:SI (reg:BI ...)) as argument. Heh.
>>> But then I'd still need to change the expansion code. I suppose this could
>>> prevent the issue with changes to code on other
On 9/28/22 09:04, Richard Sandiford wrote:
Tamar Christina writes:
Maybe the target could use (subreg:SI (reg:BI ...)) as argument. Heh.
But then I'd still need to change the expansion code. I suppose this could
prevent the issue with changes to code on other targets.
We have undocumented
Tamar Christina writes:
>> Maybe the target could use (subreg:SI (reg:BI ...)) as argument. Heh.
>
> But then I'd still need to change the expansion code. I suppose this could
> prevent the issue with changes to code on other targets.
>
>> > > We have undocumented addcc, negcc, etc. patterns,
> -Original Message-
> From: Richard Biener
> Sent: Monday, September 26, 2022 1:43 PM
> To: Tamar Christina
> Cc: gcc-patches@gcc.gnu.org; nd ; jeffreya...@gmail.com;
> Richard Sandiford
> Subject: Re: [PATCH 1/2]middle-end: RFC: On expansion of conditional
> branches, give hint if
On Mon, 26 Sep 2022, Richard Biener wrote:
> On Mon, 26 Sep 2022, Tamar Christina wrote:
>
> > > Maybe the target could use (subreg:SI (reg:BI ...)) as argument. Heh.
> >
> > But then I'd still need to change the expansion code. I suppose this could
> > prevent the issue with changes to code
On Mon, 26 Sep 2022, Tamar Christina wrote:
> > Maybe the target could use (subreg:SI (reg:BI ...)) as argument. Heh.
>
> But then I'd still need to change the expansion code. I suppose this could
> prevent the issue with changes to code on other targets.
>
> > > > We have undocumented addcc,
> Maybe the target could use (subreg:SI (reg:BI ...)) as argument. Heh.
But then I'd still need to change the expansion code. I suppose this could
prevent the issue with changes to code on other targets.
> > > We have undocumented addcc, negcc, etc. patterns, should we have aandcc
> > >
On Mon, 26 Sep 2022, Tamar Christina wrote:
> > > This pattern occurs more than 120,000 times in SPECCPU 2017 and so is
> > > quite common.
>
> > How does this help a target?
>
> So the idea is to communicate that only the bottom bit of the value is
> relevant and not the entire value itself.
> > This pattern occurs more than 120,000 times in SPECCPU 2017 and so is quite
> > common.
> How does this help a target?
So the idea is to communicate that only the bottom bit of the value is relevant
and not the entire value itself.
> Why does RTL nonzerop bits not recover thisinformation
On Fri, 23 Sep 2022, Tamar Christina wrote:
> Hi All,
>
> This is an RFC to figure out how to deal with targets that don't have native
> comparisons against QImode values.
>
> Booleans, at least in C99 and higher are 0-1 valued. This means that we only
> really need to test a single bit.
Hi All,
This is an RFC to figure out how to deal with targets that don't have native
comparisons against QImode values.
Booleans, at least in C99 and higher are 0-1 valued. This means that we only
really need to test a single bit. However in RTL we no longer have this
information available and
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