On 7/6/23 00:48, Christoph Müllner wrote:
Thanks for this!
Of course I was "lucky" and ran into the issue that the patterns did not match,
because of unexpected MULT insns where ASHIFTs were expected.
But after reading enough of combiner.cc I understood that this is on purpose
(for addresses
On Thu, Jun 29, 2023 at 4:09 PM Jeff Law wrote:
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> On 6/29/23 01:39, Christoph Müllner wrote:
> > On Wed, Jun 28, 2023 at 8:23 PM Jeff Law wrote:
> >>
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> >> On 6/28/23 06:39, Christoph Müllner wrote:
> >>
> > +;; XTheadMemIdx overview:
> > +;; All peephole passes attempt to
On 6/29/23 01:39, Christoph Müllner wrote:
On Wed, Jun 28, 2023 at 8:23 PM Jeff Law wrote:
On 6/28/23 06:39, Christoph Müllner wrote:
+;; XTheadMemIdx overview:
+;; All peephole passes attempt to improve the operand utilization of
+;; XTheadMemIdx instructions, where one sign or zero ex
On Wed, Jun 28, 2023 at 8:23 PM Jeff Law wrote:
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> On 6/28/23 06:39, Christoph Müllner wrote:
>
> >>> +;; XTheadMemIdx overview:
> >>> +;; All peephole passes attempt to improve the operand utilization of
> >>> +;; XTheadMemIdx instructions, where one sign or zero extended
> >>> +;; register-
On 6/28/23 06:39, Christoph Müllner wrote:
+;; XTheadMemIdx overview:
+;; All peephole passes attempt to improve the operand utilization of
+;; XTheadMemIdx instructions, where one sign or zero extended
+;; register-index-operand can be shifted left by a 2-bit immediate.
+;;
+;; The basic ide
On Sat, Jun 10, 2023 at 7:53 PM Jeff Law wrote:
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> On 4/28/23 00:23, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > The XTheadMemIdx ISA extension provides a additional load and store
> > instructions with new addressing modes.
> >
> > The following memory accesses types are s
On 4/28/23 00:23, Christoph Muellner wrote:
From: Christoph Müllner
The XTheadMemIdx ISA extension provides a additional load and store
instructions with new addressing modes.
The following memory accesses types are supported:
* ltype = [b,bu,h,hu,w,wu,d]
* stype = [b,h,w,d]
The following
From: Christoph Müllner
The XTheadMemIdx ISA extension provides a additional load and store
instructions with new addressing modes.
The following memory accesses types are supported:
* ltype = [b,bu,h,hu,w,wu,d]
* stype = [b,h,w,d]
The following addressing modes are supported:
* immediate offse
