Patch 12 of 14 (https://gcc.gnu.org/ml/gcc-patches/2014-09/msg01475.html) will break bigendian targets implementing vec_shr. This is a MIPS parallel of patch 13 of 14 (https://gcc.gnu.org/ml/gcc-patches/2014-09/msg01477.html) forAArch64; the idea is that vec_shr should be unaffected on little-endian, but reversed (to be the same as the old vec_shl) if big-endian.
Manual inspection of assembler output looks to do the right sort of thing on mips and mips64, but I haven't been able to run any testcases so this is not definitive. I'm hoping it is nonetheless helpful as a starting point!
gcc/ChangeLog: * config/mips/loongson.md (unspec): Remove UNSPEC_LOONGSON_DSLL. (vec_shl_<mode>): Remove. (vec_shr_<mode>): Reverse shift if BYTES_BIG_ENDIAN.
diff --git a/gcc/config/mips/loongson.md b/gcc/config/mips/loongson.md index 474033d1e2c244d3b70ad5ed630ab9f29d5fd5f6..dcba23440a5cb8cf0f2063ee15fbcf9d2a579714 100644 --- a/gcc/config/mips/loongson.md +++ b/gcc/config/mips/loongson.md @@ -39,7 +39,6 @@ UNSPEC_LOONGSON_PUNPCKL UNSPEC_LOONGSON_PADDD UNSPEC_LOONGSON_PSUBD - UNSPEC_LOONGSON_DSLL UNSPEC_LOONGSON_DSRL ]) @@ -834,22 +833,18 @@ }) ;; Whole vector shifts, used for reduction epilogues. -(define_insn "vec_shl_<mode>" - [(set (match_operand:VWHBDI 0 "register_operand" "=f") - (unspec:VWHBDI [(match_operand:VWHBDI 1 "register_operand" "f") - (match_operand:SI 2 "register_operand" "f")] - UNSPEC_LOONGSON_DSLL))] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "dsll\t%0,%1,%2" - [(set_attr "type" "fcvt")]) - (define_insn "vec_shr_<mode>" [(set (match_operand:VWHBDI 0 "register_operand" "=f") (unspec:VWHBDI [(match_operand:VWHBDI 1 "register_operand" "f") (match_operand:SI 2 "register_operand" "f")] UNSPEC_LOONGSON_DSRL))] "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" - "dsrl\t%0,%1,%2" + { + if (BYTES_BIG_ENDIAN) + return "dsll\t%0,%1,%2"; + else + return "dsrl\t%0,%1,%2"; + } [(set_attr "type" "fcvt")]) (define_expand "reduc_uplus_<mode>"