This patch adds C intrinsics for Bitmanip Extension.
RISCV_BUILTIN_NO_PREFIX is a new riscv_builtin_description like RISCV_BUILTIN.
But it uses CODE_FOR_##INSN rather than CODE_FOR_riscv_##INSN.
Some of the instructions are different to spec, see
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/59 for details.
gcc/ChangeLog:
* config.gcc: Add riscv_bitmanip.h
* config/riscv/riscv-builtins.cc (AVAIL): New AVAIL.
(RISCV_BUILTIN_NO_PREFIX): new riscv_builtin_description.
* config/riscv/riscv-ftypes.def (2): New function type.
* config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN_NO_PREFIX):New
builtins.
* config/riscv/riscv_bitmanip.h: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/scalar_bitmanip_intrinsic-1.c: New test.
* gcc.target/riscv/scalar_bitmanip_intrinsic-2.c: New test.
---
gcc/config.gcc | 2 +-
gcc/config/riscv/riscv-builtins.cc | 22 ++
gcc/config/riscv/riscv-ftypes.def | 2 +
gcc/config/riscv/riscv-scalar-crypto.def | 18 ++
gcc/config/riscv/riscv_bitmanip.h | 297 ++++++++++++++++++
.../riscv/scalar_bitmanip_intrinsic-1.c | 97 ++++++
.../riscv/scalar_bitmanip_intrinsic-2.c | 115 +++++++
7 files changed, 552 insertions(+), 1 deletion(-)
create mode 100644 gcc/config/riscv/riscv_bitmanip.h
create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-2.c
diff --git a/gcc/config.gcc b/gcc/config.gcc
index d67fe8b6a6f..37e66143c53 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -548,7 +548,7 @@ riscv*)
extra_objs="${extra_objs} riscv-vector-builtins.o
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o"
d_target_objs="riscv-d.o"
- extra_headers="riscv_vector.h riscv_crypto.h"
+ extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h"
target_gtfiles="$target_gtfiles
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
;;
diff --git a/gcc/config/riscv/riscv-builtins.cc
b/gcc/config/riscv/riscv-builtins.cc
index fc3976f3ba1..3a297b3742e 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -123,6 +123,12 @@ AVAIL (clmul_zbkc32_or_zbc32, (TARGET_ZBKC || TARGET_ZBC)
&& !TARGET_64BIT)
AVAIL (clmul_zbkc64_or_zbc64, (TARGET_ZBKC || TARGET_ZBC) && TARGET_64BIT)
AVAIL (clmulr_zbc32, TARGET_ZBC && !TARGET_64BIT)
AVAIL (clmulr_zbc64, TARGET_ZBC && TARGET_64BIT)
+AVAIL (zbb, TARGET_ZBB)
+AVAIL (zbb32, TARGET_ZBB && !TARGET_64BIT)
+AVAIL (zbb64, TARGET_ZBB && TARGET_64BIT)
+AVAIL (zbb32_or_zbkb32, (TARGET_ZBKB || TARGET_ZBB) && !TARGET_64BIT)
+AVAIL (zbb64_or_zbkb64, (TARGET_ZBKB || TARGET_ZBB) && TARGET_64BIT)
+AVAIL (zbb_or_zbkb, (TARGET_ZBKB || TARGET_ZBB))
AVAIL (hint_pause, (!0))
// CORE-V AVAIL
@@ -145,6 +151,22 @@ AVAIL (cvalu, TARGET_XCVALU && !TARGET_64BIT)
{ CODE_FOR_riscv_ ## INSN, "__builtin_riscv_" NAME, \
BUILTIN_TYPE, FUNCTION_TYPE, riscv_builtin_avail_ ## AVAIL }
+/* Construct a riscv_builtin_description from the given arguments like
RISCV_BUILTIN.
+
+ INSN is the name of the associated instruction pattern, without the
+ leading CODE_FOR_.
+
+ NAME is the name of the function itself, without the leading
+ "__builtin_riscv_".
+
+ BUILTIN_TYPE and FUNCTION_TYPE are riscv_builtin_description fields.
+
+ AVAIL is the name of the availability predicate, without the leading
+ riscv_builtin_avail_. */
+#define RISCV_BUILTIN_NO_PREFIX(INSN, NAME, BUILTIN_TYPE, FUNCTION_TYPE,
AVAIL) \
+ { CODE_FOR_ ## INSN, "__builtin_riscv_" NAME, \
+ BUILTIN_TYPE, FUNCTION_TYPE, riscv_builtin_avail_ ## AVAIL }
+
/* Define __builtin_riscv_<INSN>, which is a RISCV_BUILTIN_DIRECT function
mapped to instruction CODE_FOR_riscv_<INSN>, FUNCTION_TYPE and AVAIL
are as for RISCV_BUILTIN. */
diff --git a/gcc/config/riscv/riscv-ftypes.def
b/gcc/config/riscv/riscv-ftypes.def
index 0d1e4dd061e..13221090e5f 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -39,9 +39,11 @@ DEF_RISCV_FTYPE (1, (SI, HI))
DEF_RISCV_FTYPE (2, (USI, UQI, UQI))
DEF_RISCV_FTYPE (2, (USI, UHI, UHI))
DEF_RISCV_FTYPE (2, (USI, USI, USI))
+DEF_RISCV_FTYPE (2, (USI, USI, UQI))
DEF_RISCV_FTYPE (2, (UDI, UQI, UQI))
DEF_RISCV_FTYPE (2, (UDI, UHI, UHI))
DEF_RISCV_FTYPE (2, (UDI, USI, USI))
+DEF_RISCV_FTYPE (2, (UDI, UDI, UQI))
DEF_RISCV_FTYPE (2, (UDI, UDI, USI))
DEF_RISCV_FTYPE (2, (UDI, UDI, UDI))
DEF_RISCV_FTYPE (2, (SI, USI, USI))
diff --git a/gcc/config/riscv/riscv-scalar-crypto.def
b/gcc/config/riscv/riscv-scalar-crypto.def
index 3db9ed4a03e..5e66a1131c6 100644
--- a/gcc/config/riscv/riscv-scalar-crypto.def
+++ b/gcc/config/riscv/riscv-scalar-crypto.def
@@ -78,3 +78,21 @@ RISCV_BUILTIN (sm3p1_si, "sm3p1", RISCV_BUILTIN_DIRECT,
RISCV_USI_FTYPE_USI, cry
// ZKSED
RISCV_BUILTIN (sm4ed_si, "sm4ed", RISCV_BUILTIN_DIRECT,
RISCV_USI_FTYPE_USI_USI_USI, crypto_zksed),
RISCV_BUILTIN (sm4ks_si, "sm4ks", RISCV_BUILTIN_DIRECT,
RISCV_USI_FTYPE_USI_USI_USI, crypto_zksed),
+
+
+// ZBB
+
+RISCV_BUILTIN_NO_PREFIX (clzsi2, "clz_32",
RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, zbb),
+RISCV_BUILTIN_NO_PREFIX (clzdi2, "clz_64",
RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, zbb64),
+RISCV_BUILTIN_NO_PREFIX (ctzsi2, "ctz_32",
RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, zbb),
+RISCV_BUILTIN_NO_PREFIX (ctzdi2, "ctz_64",
RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, zbb64),
+RISCV_BUILTIN_NO_PREFIX (popcountsi2, "popcount_32",
RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, zbb),
+RISCV_BUILTIN_NO_PREFIX (popcountdi2, "popcount_64",
RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, zbb64),
+RISCV_BUILTIN_NO_PREFIX (orcbsi2, "orc_b_32",
RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, zbb32),
+RISCV_BUILTIN_NO_PREFIX (orcbdi2, "orc_b_64",
RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, zbb64),
+
+// ZBKB
+RISCV_BUILTIN_NO_PREFIX (rotrsi3, "ror_32", RISCV_BUILTIN_DIRECT,
RISCV_USI_FTYPE_USI_UQI, zbb_or_zbkb),
+RISCV_BUILTIN_NO_PREFIX (rotlsi3, "rol_32", RISCV_BUILTIN_DIRECT,
RISCV_USI_FTYPE_USI_UQI, zbb_or_zbkb),
+RISCV_BUILTIN_NO_PREFIX (rotrdi3, "ror_64", RISCV_BUILTIN_DIRECT,
RISCV_UDI_FTYPE_UDI_UQI, zbb64_or_zbkb64),
+RISCV_BUILTIN_NO_PREFIX (rotldi3, "rol_64", RISCV_BUILTIN_DIRECT,
RISCV_UDI_FTYPE_UDI_UQI, zbb64_or_zbkb64),
diff --git a/gcc/config/riscv/riscv_bitmanip.h
b/gcc/config/riscv/riscv_bitmanip.h
new file mode 100644
index 00000000000..a58d3320748
--- /dev/null
+++ b/gcc/config/riscv/riscv_bitmanip.h
@@ -0,0 +1,297 @@
+/* RISC-V Bitmanip Extension intrinsics include file.
+ Copyright (C) 2023 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 3, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef __RISCV_BITMANIP_H
+#define __RISCV_BITMANIP_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(__riscv_zbb)
+
+extern __inline unsigned
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clz_32 (uint32_t x)
+{
+ return __builtin_riscv_clz_32 (x);
+}
+
+extern __inline unsigned
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_ctz_32 (uint32_t x)
+{
+ return __builtin_riscv_ctz_32 (x);
+}
+
+extern __inline unsigned
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_cpop_32 (uint32_t x)
+{
+ return __builtin_riscv_popcount_32 (x);
+}
+
+extern __inline unsigned
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_orc_b_32 (uint32_t x)
+{
+ return __builtin_riscv_orc_b_32 (x);
+}
+
+#if __riscv_xlen == 64
+
+extern __inline unsigned
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clz_64 (uint64_t x)
+{
+ return __builtin_riscv_clz_64 (x);
+}
+
+extern __inline unsigned
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_ctz_64 (uint64_t x)
+{
+ return __builtin_riscv_ctz_64 (x);
+}
+
+extern __inline unsigned
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_cpop_64 (uint64_t x)
+{
+ return __builtin_riscv_popcount_64 (x);
+}
+
+extern __inline unsigned
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_orc_b_64 (uint64_t x)
+{
+ return __builtin_riscv_orc_b_64 (x);
+}
+
+#endif
+
+#endif // ZBB
+
+#if defined(__riscv_zbb) || defined(__riscv_zbkb)
+
+extern __inline uint32_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_ror_32(uint32_t x, uint32_t shamt)
+{
+ return __builtin_riscv_ror_32 (x,shamt);
+}
+
+extern __inline uint32_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_rol_32(uint32_t x, uint32_t shamt)
+{
+ return __builtin_riscv_rol_32 (x,shamt);
+}
+
+extern __inline uint32_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_rev8_32(uint32_t x)
+{
+ return __builtin_bswap32(x);
+}
+
+#if __riscv_xlen == 64
+
+extern __inline uint64_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_ror_64(uint64_t x, uint32_t shamt)
+{
+ return __builtin_riscv_ror_64 (x,shamt);
+}
+
+extern __inline uint64_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_rol_64(uint64_t x, uint32_t shamt)
+{
+ return __builtin_riscv_rol_64 (x,shamt);
+}
+
+extern __inline uint64_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_rev8_64(uint64_t x)
+{
+ return __builtin_bswap64(x);
+}
+
+#endif
+
+#endif // ZBB || ZBKB
+
+#if defined(__riscv_zbkb)
+
+extern __inline uint32_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_brev8_32(uint32_t x)
+{
+ return __builtin_riscv_brev8(x);
+}
+
+#if __riscv_xlen == 32
+
+extern __inline uint32_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_zip_32(uint32_t x)
+{
+ return __builtin_riscv_zip(x);
+}
+
+extern __inline uint32_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_unzip_32(uint32_t x)
+{
+ return __builtin_riscv_unzip(x);
+}
+
+#endif
+
+#if __riscv_xlen == 64
+
+extern __inline uint64_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_brev8_64(uint64_t x)
+{
+ return __builtin_riscv_brev8(x);
+}
+
+#endif
+
+#endif // ZBKB
+
+#if defined(__riscv_zbc) || defined(__riscv_zbkc)
+
+extern __inline uint32_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clmul_32(uint32_t rs1, uint32_t rs2)
+{
+ return __builtin_riscv_clmul(rs1,rs2);
+}
+
+#if __riscv_xlen == 32
+
+extern __inline uint32_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clmulh_32(uint32_t rs1, uint32_t rs2)
+{
+ return __builtin_riscv_clmulh(rs1,rs2);
+}
+
+#endif
+
+#if __riscv_xlen == 64
+
+extern __inline uint64_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clmul_64(uint64_t rs1, uint64_t rs2)
+{
+ return __builtin_riscv_clmul(rs1,rs2);
+}
+
+extern __inline uint64_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clmulh_64(uint64_t rs1, uint64_t rs2)
+{
+ return __builtin_riscv_clmulh(rs1,rs2);
+}
+
+#endif
+
+#endif // ZBC || ZBKC
+
+#if defined(__riscv_zbc)
+
+#if __riscv_xlen == 32
+
+extern __inline uint32_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clmulr_32(uint32_t rs1, uint32_t rs2)
+{
+ return __builtin_riscv_clmulr(rs1,rs2);
+}
+
+#endif
+
+#if __riscv_xlen == 64
+
+extern __inline uint64_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_clmulr_64(uint64_t rs1, uint64_t rs2)
+{
+ return __builtin_riscv_clmulr(rs1,rs2);
+}
+
+#endif
+
+#endif // ZBC
+
+#if defined(__riscv_zbkx)
+
+#if __riscv_xlen == 32
+
+extern __inline uint32_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_xperm4_32(uint32_t rs1, uint32_t rs2)
+{
+ return __builtin_riscv_xperm4(rs1,rs2);
+}
+
+extern __inline uint32_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_xperm8_32(uint32_t rs1, uint32_t rs2)
+{
+ return __builtin_riscv_xperm8(rs1,rs2);
+}
+
+#endif
+
+#if __riscv_xlen == 64
+
+extern __inline uint64_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_xperm4_64(uint64_t rs1, uint64_t rs2)
+{
+ return __builtin_riscv_xperm4(rs1,rs2);
+}
+
+extern __inline uint64_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__riscv_xperm8_64(uint64_t rs1, uint64_t rs2)
+{
+ return __builtin_riscv_xperm8(rs1,rs2);
+}
+
+#endif
+
+#endif // ZBKX
+
+#if defined(__cplusplus)
+}
+#endif // __cplusplus
+#endif // __RISCV_BITMANIP_H
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-1.c
b/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-1.c
new file mode 100644
index 00000000000..6a082b8bcf2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-1.c
@@ -0,0 +1,97 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zbb_zbc_zbkb_zbkc_zbkx -mabi=ilp32d" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include "riscv_bitmanip.h"
+
+unsigned foo1(uint32_t x)
+{
+ return __riscv_clz_32(x);
+}
+
+unsigned foo2(uint32_t x)
+{
+ return __riscv_ctz_32(x);
+}
+
+unsigned foo3(uint32_t x)
+{
+ return __riscv_cpop_32(x);
+}
+
+uint32_t foo4(uint32_t x)
+{
+ return __riscv_orc_b_32(x);
+}
+
+uint32_t foo5(uint32_t x, uint32_t shamt)
+{
+ return __riscv_ror_32(x,shamt);
+}
+
+uint32_t foo6(uint32_t x, uint32_t shamt)
+{
+ return __riscv_rol_32(x,shamt);
+}
+
+uint32_t foo7(uint32_t x)
+{
+ return __riscv_rev8_32(x);
+}
+
+uint32_t foo8(uint32_t x)
+{
+ return __riscv_brev8_32(x);
+}
+
+uint32_t foo9(uint32_t x)
+{
+ return __riscv_zip_32(x);
+}
+
+uint32_t foo10(uint32_t x)
+{
+ return __riscv_unzip_32(x);
+}
+
+uint32_t foo11(uint32_t rs1,uint32_t rs2)
+{
+ return __riscv_clmul_32(rs1,rs2);
+}
+
+uint32_t foo12(uint32_t rs1,uint32_t rs2)
+{
+ return __riscv_clmulh_32(rs1,rs2);
+}
+
+uint32_t foo13(uint32_t rs1,uint32_t rs2)
+{
+ return __riscv_clmulr_32(rs1,rs2);
+}
+
+uint32_t foo14(uint32_t rs1,uint32_t rs2)
+{
+ return __riscv_xperm4_32(rs1,rs2);
+}
+
+uint32_t foo15(uint32_t rs1,uint32_t rs2)
+{
+ return __riscv_xperm8_32(rs1,rs2);
+}
+
+/* { dg-final { scan-assembler-times "clz" 1 } } */
+/* { dg-final { scan-assembler-times "ctz" 1 } } */
+/* { dg-final { scan-assembler-times "cpop" 1 } } */
+/* { dg-final { scan-assembler-times "orc.b" 1 } } */
+/* { dg-final { scan-assembler-times "ror" 1 } } */
+/* { dg-final { scan-assembler-times "rol" 1 } } */
+/* { dg-final { scan-assembler-times {\mrev8} 1 } } */
+/* { dg-final { scan-assembler-times {\mbrev8} 1 } } */
+/* { dg-final { scan-assembler-times {\mzip} 1 } } */
+/* { dg-final { scan-assembler-times {\munzip} 1 } } */
+/* { dg-final { scan-assembler-times "clmul\t" 1 } } */
+/* { dg-final { scan-assembler-times "clmulh" 1 } } */
+/* { dg-final { scan-assembler-times "clmulr" 1 } } */
+/* { dg-final { scan-assembler-times "xperm4" 1 } } */
+/* { dg-final { scan-assembler-times "xperm8" 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-2.c
b/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-2.c
new file mode 100644
index 00000000000..a9c24520e59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-2.c
@@ -0,0 +1,115 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zbb_zbc_zbkb_zbkc_zbkx -mabi=lp64d" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include "riscv_bitmanip.h"
+
+unsigned foo1(uint32_t x)
+{
+ return __riscv_clz_32(x);
+}
+
+unsigned foo2(uint32_t x)
+{
+ return __riscv_ctz_32(x);
+}
+
+unsigned foo3(uint32_t x)
+{
+ return __riscv_cpop_32(x);
+}
+
+unsigned long foo4(uint32_t x, uint8_t shamt)
+{
+ return __riscv_ror_32(x,shamt);
+}
+
+unsigned long foo5(uint32_t x, uint8_t shamt)
+{
+ return __riscv_rol_32(x,shamt);
+}
+
+unsigned foo6(uint64_t x)
+{
+ return __riscv_clz_64(x);
+}
+
+unsigned foo7(uint64_t x)
+{
+ return __riscv_ctz_64(x);
+}
+
+unsigned foo8(uint64_t x)
+{
+ return __riscv_cpop_64(x);
+}
+
+uint64_t foo9(uint64_t x)
+{
+ return __riscv_orc_b_64(x);
+}
+
+uint64_t foo10(uint64_t rs1, uint8_t rs2)
+{
+ return __riscv_ror_64(rs1,rs2);
+}
+
+uint64_t foo11(uint64_t rs1, uint8_t rs2)
+{
+ return __riscv_rol_64(rs1,rs2);
+}
+
+uint64_t foo12(uint64_t x)
+{
+ return __riscv_rev8_64(x);
+}
+
+uint64_t foo13(uint64_t x)
+{
+ return __riscv_brev8_64(x);
+}
+
+uint64_t foo14(uint64_t rs1,uint64_t rs2)
+{
+ return __riscv_clmul_64(rs1,rs2);
+}
+
+uint64_t foo15(uint64_t rs1,uint64_t rs2)
+{
+ return __riscv_clmulh_64(rs1,rs2);
+}
+
+uint64_t foo16(uint64_t rs1,uint64_t rs2)
+{
+ return __riscv_clmulr_64(rs1,rs2);
+}
+
+uint64_t foo17(uint64_t rs1,uint64_t rs2)
+{
+ return __riscv_xperm4_64(rs1,rs2);
+}
+
+uint64_t foo18(uint64_t rs1,uint64_t rs2)
+{
+ return __riscv_xperm8_64(rs1,rs2);
+}
+
+/* { dg-final { scan-assembler-times "clzw" 1 } } */
+/* { dg-final { scan-assembler-times "ctzw" 1 } } */
+/* { dg-final { scan-assembler-times "cpopw" 1 } } */
+/* { dg-final { scan-assembler-times "rorw" 1 } } */
+/* { dg-final { scan-assembler-times "rolw" 1 } } */
+/* { dg-final { scan-assembler-times "clz\t" 1 } } */
+/* { dg-final { scan-assembler-times "ctz\t" 1 } } */
+/* { dg-final { scan-assembler-times "cpop\t" 1 } } */
+/* { dg-final { scan-assembler-times "orc.b" 1 } } */
+/* { dg-final { scan-assembler-times "ror\t" 1 } } */
+/* { dg-final { scan-assembler-times "rol\t" 1 } } */
+/* { dg-final { scan-assembler-times {\mrev8} 1 } } */
+/* { dg-final { scan-assembler-times {\mbrev8} 1 } } */
+/* { dg-final { scan-assembler-times "clmul\t" 1 } } */
+/* { dg-final { scan-assembler-times "clmulh" 1 } } */
+/* { dg-final { scan-assembler-times "clmulr" 1 } } */
+/* { dg-final { scan-assembler-times "xperm4" 1 } } */
+/* { dg-final { scan-assembler-times "xperm8" 1 } } */
+
--
2.34.1
