This patch introduces a new value for the insn type attribute viscmp. VIS comparison insn are adapted to use it, and finally the DFA schedulers are updated accordingly.
gcc/ChangeLog: * config/sparc/sparc.md ("type"): New insn type viscmp. ("fcmp<gcond:code><GCM:gcm_name><P:mode>_vis"): Set insn type to viscmp. ("fpcmp<gcond:code>8<P:mode>_vis"): Likewise. ("fucmp<gcond:code>8<P:mode>_vis"): Likewise. ("fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis"): Likewise. * config/sparc/niagara7.md ("n7_vis_logical_v3pipe"): Handle viscmp. ("n7_vis_logical_11cycle"): Likewise. * config/sparc/niagara4.md ("n4_vis_logical"): Likewise. * config/sparc/niagara2.md ("niag3_vis": Likewise. * config/sparc/niagara.md ("niag_vis"): Likewise. * config/sparc/ultra3.md ("us3_fga"): Likewise. * config/sparc/ultra1_2.md ("us1_fga_double"): Likewise. --- gcc/ChangeLog | 17 +++++++++++++++++ gcc/config/sparc/niagara.md | 2 +- gcc/config/sparc/niagara2.md | 4 ++-- gcc/config/sparc/niagara4.md | 5 +++-- gcc/config/sparc/niagara7.md | 4 ++-- gcc/config/sparc/sparc.md | 15 ++++++--------- gcc/config/sparc/ultra1_2.md | 8 ++++---- gcc/config/sparc/ultra3.md | 2 +- 8 files changed, 36 insertions(+), 21 deletions(-) diff --git a/gcc/config/sparc/niagara.md b/gcc/config/sparc/niagara.md index f9a1f6d..a8e23b8 100644 --- a/gcc/config/sparc/niagara.md +++ b/gcc/config/sparc/niagara.md @@ -114,5 +114,5 @@ */ (define_insn_reservation "niag_vis" 8 (and (eq_attr "cpu" "niagara") - (eq_attr "type" "fga,visl,vismv,fgm_pack,fgm_mul,pdist,edge,edgen,gsr,array,bmask")) + (eq_attr "type" "fga,visl,viscmp,vismv,fgm_pack,fgm_mul,pdist,edge,edgen,gsr,array,bmask")) "niag_pipe*8") diff --git a/gcc/config/sparc/niagara2.md b/gcc/config/sparc/niagara2.md index 34ee630..3190d55 100644 --- a/gcc/config/sparc/niagara2.md +++ b/gcc/config/sparc/niagara2.md @@ -111,10 +111,10 @@ (define_insn_reservation "niag2_vis" 6 (and (eq_attr "cpu" "niagara2") - (eq_attr "type" "fga,vismv,visl,fgm_pack,fgm_mul,pdist,edge,edgen,array,bmask,gsr")) + (eq_attr "type" "fga,vismv,visl,viscmp,fgm_pack,fgm_mul,pdist,edge,edgen,array,bmask,gsr")) "niag2_pipe*6") (define_insn_reservation "niag3_vis" 9 (and (eq_attr "cpu" "niagara3") - (eq_attr "type" "fga,vismv,visl,fgm_pack,fgm_mul,pdist,pdistn,edge,edgen,array,bmask,gsr")) + (eq_attr "type" "fga,vismv,visl,viscmp,fgm_pack,fgm_mul,pdist,pdistn,edge,edgen,array,bmask,gsr")) "niag2_pipe*9") diff --git a/gcc/config/sparc/niagara4.md b/gcc/config/sparc/niagara4.md index cc1bb75..a3417d2 100644 --- a/gcc/config/sparc/niagara4.md +++ b/gcc/config/sparc/niagara4.md @@ -90,8 +90,9 @@ (define_insn_reservation "n4_vis_logical" 3 (and (eq_attr "cpu" "niagara4") - (and (eq_attr "type" "visl,pdistn") - (eq_attr "fptype" "double"))) + (ior (and (eq_attr "type" "visl,pdistn") + (eq_attr "fptype" "double")) + (eq_attr "type" "viscmp"))) "n4_slot1, nothing*2") (define_insn_reservation "n4_vis_logical_11cycle" 11 diff --git a/gcc/config/sparc/niagara7.md b/gcc/config/sparc/niagara7.md index 3dc8f9e..3f46198 100644 --- a/gcc/config/sparc/niagara7.md +++ b/gcc/config/sparc/niagara7.md @@ -123,13 +123,13 @@ (define_insn_reservation "n7_vis_logical_v3pipe" 11 (and (eq_attr "cpu" "niagara7") - (and (eq_attr "type" "visl,pdistn") + (and (eq_attr "type" "visl,viscmp,pdistn") (eq_attr "v3pipe" "true"))) "n7_slot1, nothing*2") (define_insn_reservation "n7_vis_logical_11cycle" 11 (and (eq_attr "cpu" "niagara7") - (and (eq_attr "type" "visl") + (and (eq_attr "type" "visl,viscmp") (eq_attr "v3pipe" "false"))) "n7_slot1, nothing*10") diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index da23060..04da8ae 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -281,7 +281,8 @@ fpcmp, fpmul,fpdivs,fpdivd, fpsqrts,fpsqrtd, - fga,visl,vismv,fgm_pack,fgm_mul,pdist,pdistn,edge,edgen,gsr,array,bmask, + fga,visl,vismv,viscmp, + fgm_pack,fgm_mul,pdist,pdistn,edge,edgen,gsr,array,bmask, cmove, ialuX, multi,savew,flushw,iflush,trap,lzd" @@ -9059,8 +9060,7 @@ UNSPEC_FCMP))] "TARGET_VIS" "fcmp<gcond:code><GCM:gcm_name>\t%1, %2, %0" - [(set_attr "type" "visl") - (set_attr "fptype" "double") + [(set_attr "type" "viscmp") (set_attr "v3pipe" "true")]) (define_insn "fpcmp<gcond:code>8<P:mode>_vis" @@ -9070,8 +9070,7 @@ UNSPEC_FCMP))] "TARGET_VIS4" "fpcmp<gcond:code>8\t%1, %2, %0" - [(set_attr "type" "visl") - (set_attr "fptype" "double")]) + [(set_attr "type" "viscmp")]) (define_expand "vcond<GCM:mode><GCM:mode>" [(match_operand:GCM 0 "register_operand" "") @@ -9427,8 +9426,7 @@ UNSPEC_FUCMP))] "TARGET_VIS3" "fucmp<gcond:code>8\t%1, %2, %0" - [(set_attr "type" "visl") - (set_attr "v3pipe" "true")]) + [(set_attr "type" "viscmp")]) (define_insn "fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis" [(set (match_operand:P 0 "register_operand" "=r") @@ -9437,8 +9435,7 @@ UNSPEC_FUCMP))] "TARGET_VIS4" "fpcmpu<gcond:code><GCM:gcm_name>\t%1, %2, %0" - [(set_attr "type" "visl") - (set_attr "fptype" "double")]) + [(set_attr "type" "viscmp")]) (define_insn "*naddsf3" [(set (match_operand:SF 0 "register_operand" "=f") diff --git a/gcc/config/sparc/ultra1_2.md b/gcc/config/sparc/ultra1_2.md index 6af2859..a4fb883 100644 --- a/gcc/config/sparc/ultra1_2.md +++ b/gcc/config/sparc/ultra1_2.md @@ -263,10 +263,10 @@ (define_insn_reservation "us1_fga_double" 2 - (and (and - (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fga,visl,vismv")) - (eq_attr "fptype" "double")) + (and (eq_attr "cpu" "ultrasparc") + (ior (and (eq_attr "type" "fga,visl,vismv") + (eq_attr "fptype" "double")) + (eq_attr "type" "viscmp"))) "us1_fpa + us1_fp_double + us1_slotany, nothing") (define_bypass 1 "us1_fga_double" "us1_fga_double") diff --git a/gcc/config/sparc/ultra3.md b/gcc/config/sparc/ultra3.md index f5b81d6..db20cd9 100644 --- a/gcc/config/sparc/ultra3.md +++ b/gcc/config/sparc/ultra3.md @@ -176,7 +176,7 @@ (define_insn_reservation "us3_fga" 3 (and (eq_attr "cpu" "ultrasparc3") - (eq_attr "type" "fga,visl,vismv")) + (eq_attr "type" "fga,visl,viscmp,vismv")) "us3_fpa + us3_slotany, nothing*2") (define_insn_reservation "us3_fgm" -- 2.3.4