RE: [PATCH V16] VECT: Add decrement IV iteration loop control by variable amount support

2023-05-25 Thread Li, Pan2 via Gcc-patches
Committed, thanks Richard. Pan -Original Message- From: Gcc-patches On Behalf Of Richard Biener via Gcc-patches Sent: Thursday, May 25, 2023 9:06 PM To: Richard Sandiford Cc: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org Subject: Re: [PATCH V16] VECT: Add decrement IV iteration loop

Re: [PATCH V16] VECT: Add decrement IV iteration loop control by variable amount support

2023-05-25 Thread Richard Biener via Gcc-patches
On Thu, 25 May 2023, Richard Sandiford wrote: > This looks good to me. Just a couple of very minor cosmetic things: > > juzhe.zh...@rivai.ai writes: > > @@ -753,17 +846,35 @@ vect_set_loop_condition_partial_vectors (class loop > > *loop, > > continue; > > } > > > > - /* See

Re: Re: [PATCH V16] VECT: Add decrement IV iteration loop control by variable amount support

2023-05-25 Thread 钟居哲
ubject: Re: [PATCH V16] VECT: Add decrement IV iteration loop control by variable amount support This looks good to me. Just a couple of very minor cosmetic things: juzhe.zh...@rivai.ai writes: > @@ -753,17 +846,35 @@ vect_set_loop_condition_partial_vectors (class loop > *loop, &

Re: [PATCH V16] VECT: Add decrement IV iteration loop control by variable amount support

2023-05-25 Thread Richard Sandiford via Gcc-patches
This looks good to me. Just a couple of very minor cosmetic things: juzhe.zh...@rivai.ai writes: > @@ -753,17 +846,35 @@ vect_set_loop_condition_partial_vectors (class loop > *loop, > continue; > } > > - /* See whether zero-based IV would ever generate all-false masks >

[PATCH V16] VECT: Add decrement IV iteration loop control by variable amount support

2023-05-25 Thread juzhe . zhong
From: Ju-Zhe Zhong This patch is supporting decrement IV by following the flow designed by Richard: (1) In vect_set_loop_condition_partial_vectors, for the first iteration of: call vect_set_loop_controls_directly. (2) vect_set_loop_controls_directly calculates "step" as in your patch. If rg