On 8/3/25 8:19 PM, Li, Pan2 wrote:
Thanks Jeff.
OK. Any change we could get run test for this in addition to the scanners?
I tried to add run test target this but seems happen to work here for mulhsu.
Here we only cares the result(high bits of mul) has values or not, looks like
mulhsu wi
v1] RISC-V: Fix scalar code-gen of unsigned SAT_MUL
On 7/30/25 11:22 PM, pan2...@intel.com wrote:
> From: Pan Li
>
> The previous code-gen of scalar unsigned SAT_MUL, aka usmul.
> Leverage the mulhs by mistake, it should be mulhu for the
> hight bit result of mul. Thus, this patch
On 7/30/25 11:22 PM, pan2...@intel.com wrote:
From: Pan Li
The previous code-gen of scalar unsigned SAT_MUL, aka usmul.
Leverage the mulhs by mistake, it should be mulhu for the
hight bit result of mul. Thus, this patch would like to make
it correct.
gcc/ChangeLog:
* config/riscv/
From: Pan Li
The previous code-gen of scalar unsigned SAT_MUL, aka usmul.
Leverage the mulhs by mistake, it should be mulhu for the
hight bit result of mul. Thus, this patch would like to make
it correct.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_xmode_usmul): Take
u
