Committed, thanks Robin.
Pan
-Original Message-
From: Robin Dapp
Sent: Tuesday, June 11, 2024 4:19 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com
Subject: Re: [PATCH v1] RISC-V: Implement .SAT_SUB
Thanks, the patch is OK then.
Regards
Robin
nu.org
Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com
Subject: Re: [PATCH v1] RISC-V: Implement .SAT_SUB for unsigned vector int
Hi Pan,
in general LGTM. Would you mind adding the coremark-pro
testcase which should be working now, and, was the original
r
Hi Pan,
in general LGTM. Would you mind adding the coremark-pro
testcase which should be working now, and, was the original
reason for doing this?
I believe the following should do:
extern int wsize;
typedef unsigned short Posf;
#define NIL 0
void foo (Posf *p)
{
register unsigned n, m;
d
From: Pan Li
As the middle support of .SAT_SUB committed, implement the unsigned
vector int of .SAT_SUB for the riscv backend. Consider below example
code:
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit
